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91. 发明授权

US08380777B2 Normal-basis to canonical-basis transformation for binary galois-fields GF(2m) 有权
标题翻译：二进制Galois-field的典型基变换法（2m）
公开(公告)号：US08380777B2
公开(公告)日：2013-02-19
申请号：US11772176
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.
摘要翻译：对于通用多项式和以所有形式的所有形式的特殊不可约多项式提供了从正常形式到规范形式的基础转换，称为全要素多项式（AOP）。通过在飞行中创建矩阵，或者通过提供以最小的硬件扩展来计算结果的替代方法来最小化大矩阵的生成和存储。

92. 发明授权

US07986779B2 Efficient elliptic-curve cryptography based on primality of the order of the ECC-group 有权
标题翻译：基于ECC组的顺序的有效椭圆曲线加密
公开(公告)号：US07986779B2
公开(公告)日：2011-07-26
申请号：US11772170
申请日：2007-06-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28 , G06F7/72
CPC分类号： G06F7/725 , G06F5/01
摘要： Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.
摘要翻译：通过最小化移位操作的数量来减少执行用于ECC的标量点乘法的时间。通过基于ECC组的顺序的基本原理执行中间计算的点的选择性比较，通过应用模量缩放来最小化这些操作。

93. 发明申请

US20100153829A1 RESIDUE GENERATION 失效
标题翻译：残留生成
公开(公告)号：US20100153829A1
公开(公告)日：2010-06-17
申请号：US12336029
申请日：2008-12-16
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi Feghali
IPC分类号： H03M13/09 , G06F7/72 , G06F11/10
CPC分类号： G06F7/724 , H03M13/091
摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.
摘要翻译：在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少是乘法的结果。所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

94. 发明授权

US07539718B2 Method and apparatus for performing Montgomery multiplications 失效
标题翻译：执行蒙哥马利乘法的方法和装置
公开(公告)号：US07539718B2
公开(公告)日：2009-05-26
申请号：US10944354
申请日：2004-09-16
申请人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
发明人： Kamal J. Koshy , Gilbert Wolrich , Jaroslaw J. Sydir , Wajdi K. Feghali
IPC分类号： G06F7/38
CPC分类号： G06F7/728 , G06F2207/3884
摘要： An arrangement is provided for performing Montgomery multiplications. A Montgomery multiplication comprises a plurality of iterations of basic operations (e.g., carry-save additions), and is performed by a Montgomery multiplication engine (MME). Basic operations in each iteration may be performed by multiple Montgomery multiplication processing elements (MMPEs). An MME may be arranged to pipeline the process of performing iterations of multiple basic operations and other operations required to complete a Montgomery multiplication both horizontally and vertically. An MME may also be arranged to interleave processes of performing two Montgomery multiplications.
摘要翻译：提供了执行蒙哥马利乘法的安排。蒙哥马利乘法包括多个基本操作的迭代（例如，进位保存添加），并且由蒙哥马利乘法引擎（MME）执行。每个迭代中的基本操作可以由多个蒙哥马利乘法处理元件（MMPE）执行。 MME可以被布置成管理执行多个基本操作的迭代的过程以及完成水平和垂直的蒙哥马利乘法所需的其他操作。还可以将MME布置成交织执行两个蒙哥马利乘法的处理。

95. 发明授权

US07426215B2 Method and apparatus for scheduling packets 有权
标题翻译：调度数据包的方法和装置
公开(公告)号：US07426215B2
公开(公告)日：2008-09-16
申请号：US10819428
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L47/50 , H04L47/527
摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.
摘要翻译：一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的置位，以识别要出列的分组。

96. 发明授权

US07325099B2 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US07325099B2
公开(公告)日：2008-01-29
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

97. 发明申请

US20050251642A1 Data alignment micro-architecture systems and methods 失效
标题翻译：数据对齐微架构系统和方法
公开(公告)号：US20050251642A1
公开(公告)日：2005-11-10
申请号：US10838078
申请日：2004-05-03
申请人： Jose Niell , Gilbert Wolrich , Thomas Dmukauskas , Mark Rosenbluth
发明人： Jose Niell , Gilbert Wolrich , Thomas Dmukauskas , Mark Rosenbluth
IPC分类号： G06F9/312 , G06F9/38 , G06F12/00 , G06F12/04
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3816 , G06F9/3842 , G06F12/04
摘要： Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an indication to the shifter of an amount by which the data is to be shifted. In one embodiment, the control logic provides support for speculative execution. The control logic may also permit multiplexing of big endian and little endian data alignment operations, and/or multiplexing of data alignment operations with non-data alignment operations. In one embodiment, the memory unit, shifter, and control logic are integrated within a processing unit, such as a microengine in a network processor.
摘要翻译：公开了用于在存储器访问和其他应用中对准数据的系统和方法。在一个实施例中，提供了一种系统，其包括存储器单元，移位器和可操作以将数据从存储器单元路由到移位器的控制逻辑，并向移位器发送数据要被移位的量的指示。在一个实施例中，控制逻辑提供对推测执行的支持。控制逻辑还可以允许大端和小端数据对准操作的复用，和/或数据对准操作与非数据对准操作的复用。在一个实施例中，存储器单元，移位器和控制逻辑集成在处理单元内，诸如网络处理器中的微引擎。

98. 发明申请

US20050149744A1 Network processor having cryptographic processing including an authentication buffer 审中-公开
标题翻译：具有加密处理的网络处理器，包括认证缓冲器
公开(公告)号：US20050149744A1
公开(公告)日：2005-07-07
申请号：US10749913
申请日：2003-12-29
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： G06F21/00 , H04L9/32 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , H04L9/32 , H04L63/08
摘要： A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.
摘要翻译：具有加密处理的网络处理包括用于存储加密数据并将加密数据提供给认证核心的认证缓冲器。

99. 发明申请

US20050038793A1 Circular link list scheduling 有权
标题翻译：循环链表调度
公开(公告)号：US20050038793A1
公开(公告)日：2005-02-17
申请号：US10641324
申请日：2003-08-14
申请人： David Romano , Gilbert Wolrich , Donald Hooper
发明人： David Romano , Gilbert Wolrich , Donald Hooper
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L49/254 , H04L47/50 , H04L47/568
摘要： A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.
摘要翻译：控制诸如可变大小分组或固定大小小区之类的数据单元的传输到诸如交换结构系统的网络设备的端口的调度机制。调度机制维护调度数据结构，包括根据服务类别存储可用队列的信息和表示可用端口队列的非空端口队列的循环缓冲区。调度机制使用数据结构来做出关于非空端口队列中的数据单元的调度的调度决定，以传送到端口。

100. 发明申请

US20050018601A1 Traffic management 审中-公开
标题翻译：交通管理
公开(公告)号：US20050018601A1
公开(公告)日：2005-01-27
申请号：US10612552
申请日：2003-07-01
申请人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
发明人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
IPC分类号： H04L12/56 , H04Q11/04 , H04L1/00
CPC分类号： H04L12/5601 , H04L2012/561 , H04L2012/5636 , H04L2012/5679
摘要： In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.
摘要翻译：一般来说，一方面，本公开描述了一种处理通过网络接收的分组的系统。该系统包括网络处理器的至少一个线程的接收处理，以接收属于不同流的分组的数据。系统还包括至少一个线程的发送过程，以发送由接收过程接收的分组。至少部分地基于与不同流相关联的服务质量特征，至少一个线程的调度器过程填充至少一个流服务调度。计划确定不同的候选候选人的服务。该系统还包括至少一个线程的整形过程，以从候选流中选择来自至少一个调度的服务。

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