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91. 发明申请

US20050149744A1 Network processor having cryptographic processing including an authentication buffer 审中-公开
标题翻译：具有加密处理的网络处理器，包括认证缓冲器
公开(公告)号：US20050149744A1
公开(公告)日：2005-07-07
申请号：US10749913
申请日：2003-12-29
申请人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
发明人： Jaroslaw Sydir , Kamal Koshy , Wajdi Feghali , Bradley Burres , Gilbert Wolrich
IPC分类号： G06F21/00 , H04L9/32 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , H04L9/32 , H04L63/08
摘要： A network processing having cryptographic processing includes an authentication buffer for storing ciphered data and providing the ciphered data to an authentication core.
摘要翻译：具有加密处理的网络处理包括用于存储加密数据并将加密数据提供给认证核心的认证缓冲器。

92. 发明申请

US20050038793A1 Circular link list scheduling 有权
标题翻译：循环链表调度
公开(公告)号：US20050038793A1
公开(公告)日：2005-02-17
申请号：US10641324
申请日：2003-08-14
申请人： David Romano , Gilbert Wolrich , Donald Hooper
发明人： David Romano , Gilbert Wolrich , Donald Hooper
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L49/254 , H04L47/50 , H04L47/568
摘要： A scheduling mechanism to control transmission of data units, such as variable size packets or fixed size cells, to ports of a network device such as a switching fabric system. The scheduling mechanism maintains scheduling data structures, including an array storing information for available queues of ports and circular buffers representing nonempty port queues of the available port queues according to classes of service. The scheduling mechanism uses the data structures to make scheduling decisions concerning the scheduling of data units in the nonempty port queues for transmission to the ports.
摘要翻译：控制诸如可变大小分组或固定大小小区之类的数据单元的传输到诸如交换结构系统的网络设备的端口的调度机制。调度机制维护调度数据结构，包括根据服务类别存储可用队列的信息和表示可用端口队列的非空端口队列的循环缓冲区。调度机制使用数据结构来做出关于非空端口队列中的数据单元的调度的调度决定，以传送到端口。

93. 发明申请

US20050018601A1 Traffic management 审中-公开
标题翻译：交通管理
公开(公告)号：US20050018601A1
公开(公告)日：2005-01-27
申请号：US10612552
申请日：2003-07-01
申请人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
发明人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
IPC分类号： H04L12/56 , H04Q11/04 , H04L1/00
CPC分类号： H04L12/5601 , H04L2012/561 , H04L2012/5636 , H04L2012/5679
摘要： In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.
摘要翻译：一般来说，一方面，本公开描述了一种处理通过网络接收的分组的系统。该系统包括网络处理器的至少一个线程的接收处理，以接收属于不同流的分组的数据。系统还包括至少一个线程的发送过程，以发送由接收过程接收的分组。至少部分地基于与不同流相关联的服务质量特征，至少一个线程的调度器过程填充至少一个流服务调度。计划确定不同的候选候选人的服务。该系统还包括至少一个线程的整形过程，以从候选流中选择来自至少一个调度的服务。

94. 发明授权

US06728845B2 SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues 有权
标题翻译：用于并行处理器架构的SRAM控制器和用于使用读取/读取队列控制对RAM的访问的方法
公开(公告)号：US06728845B2
公开(公告)日：2004-04-27
申请号：US10208264
申请日：2002-07-30
申请人： Matthew J. Adiletta , William Wheeler , James Redfield , Daniel Cutter , Gilbert Wolrich
发明人： Matthew J. Adiletta , William Wheeler , James Redfield , Daniel Cutter , Gilbert Wolrich
IPC分类号： G06F1300
CPC分类号： G06F13/1642
摘要： A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.
摘要翻译：用于诸如静态RAM（SRAM）的随机存取存储器（RAM）的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。地址和命令队列包括存储读取存储器引用的读取队列。控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用排队。存储器控制器可以在并行处理系统中使用，并且还可以包括订单队列，锁定查找内容可寻址存储器（CAM）和读锁定失败队列。还描述了包括媒体访问控制器（MAC），网络处理器和SRAM控制器的系统以及用于控制RAM的方法。

95. 发明授权

US5796976A Temporary storage having entries smaller than memory bus 失效
标题翻译：临时存储的条目小于内存总线
公开(公告)号：US5796976A
公开(公告)日：1998-08-18
申请号：US590214
申请日：1996-01-23
申请人： Bhavin Shah , Era Nangia , Gilbert Wolrich , Nital Patwa
发明人： Bhavin Shah , Era Nangia , Gilbert Wolrich , Nital Patwa
IPC分类号： G06F7/78 , G06F13/00 , G06F13/14
CPC分类号： G06F7/78
摘要： Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.
摘要翻译：信息存储在临时存储器中，随后通过总线传送到存储器。临时存储设置有多个条目，每个条目具有小于总线大小的所选大小。为存储器的公共区域指定的信息存储在不同的条目中，并且不同的条目被链接。在转移到内存之前，汇编来自链接条目的信息。然后将汇编的信息通过总线传送到存储器。临时存储器的实施例包括写入队列和写入缓冲器。

96. 发明授权

US4623981A ALU with carry length detection 失效
标题翻译： ALU带进位长度检测
公开(公告)号：US4623981A
公开(公告)日：1986-11-18
申请号：US534018
申请日：1983-09-20
申请人： Gilbert Wolrich , Edward J. McLellan , Robert Yodlowski , Daniel Dobberpuhl
发明人： Gilbert Wolrich , Edward J. McLellan , Robert Yodlowski , Daniel Dobberpuhl
IPC分类号： G06F7/50 , G06F7/505 , G06F7/508 , G06F1/04
CPC分类号： G06F7/5052
摘要： An ALU, performing selected operations on input operands in a predetermined clock cycle, uses means for detecting a carry propagation path greater than a predetermined number of consecutive bit positions to cause a stretching of the clock cycle. Since such a long carry propagation path is detected for only a very small percentage of all operations, the cycle is normally shorter than otherwise possible, AND, thus, the performance of a system using such an improved ALU is increased.
摘要翻译：在预定时钟周期中对输入操作数执行选择的操作的ALU使用用于检测大于预定数量的连续位位置的进位传播路径的装置以引起时钟周期的延长。由于这种长的进位传播路径仅在所有操作中只有非常小的百分比被检测到，所以该循环通常比其他可能的更短。因此，使用这种改进的ALU的系统的性能提高。

97. 发明授权

US08391475B2 Method and apparatus for advanced encryption standard (AES) block cipher 有权
标题翻译：高级加密标准（AES）块密码的方法和装置
公开(公告)号：US08391475B2
公开(公告)日：2013-03-05
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04K1/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译：可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。此外，延迟可能隐藏在非关键的最后一轮。

98. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

99. 发明授权

US08042025B2 Determining a message residue 有权
标题翻译：确定消息残差
公开(公告)号：US08042025B2
公开(公告)日：2011-10-18
申请号：US12291621
申请日：2008-11-12
申请人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
发明人： Vinodh Gopal , Gilbert Wolrich , Wajdi Feghali , Erdinc Ozturk , Shay Gueron
IPC分类号： H03M13/03
CPC分类号： G06F7/724 , H03M13/091
摘要： In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit reflection and shift of a third number having an endian format opposite to that of the first endian format, and perform a polynomial multiplication of the first number and the at least a portion of the first number.
摘要翻译：在一个方面，用于确定相对于包括一系列段的消息的多项式的模块余数的电路。在另一方面，访问具有第一末端格式的第一号码的至少一部分的电路基于具有与第一末端格式相反的端格式的第三号码的位反射和位移来确定第二号码，以及执行第一数字和第一数字的至少一部分的多项式相乘。

100. 发明申请

US20100205455A1 DIFFUSION AND CRYPTOGRAPHIC-RELATED OPERATIONS 有权
标题翻译：扩展和与CRIPTO图相关的操作
公开(公告)号：US20100205455A1
公开(公告)日：2010-08-12
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： H04L9/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

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