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    • 91. 发明申请
    • USE OF DATA LATCHES IN MULTI-PHASE PROGRAMMING OF NON-VOLATILE MEMORIES
    • 数据锁存器在非易失性存储器的多阶段编程中的应用
    • WO2006107633A1
    • 2006-10-12
    • PCT/US2006/011032
    • 2006-03-27
    • SANDISK CORPORATIONLI, YanCERNEA, Raul-Adrian
    • LI, YanCERNEA, Raul-Adrian
    • G11C16/34
    • G11C16/3468
    • A non-volatile memory device includes circuitry for governing a multi-phase programming process in a non-volatile memory. The exemplary embodiment uses a quick pass write technique where a single programming pass is used, but the biasing of the selected memory cells is altered to slow programming as the memory cells approach their target values by raising the voltage level of the channels of the selected memory cells. A principle aspect of the present invention introduces a latch associated with the read/write circuitry connectable to each selected memory cell along a corresponding bit line for the storage of the result of the verify at this lower level.
    • 非易失性存储器件包括用于在非易失性存储器中控制多相编程过程的电路。 示例性实施例使用快速通过写入技术,其中使用单个编程遍,但是当存储器单元通过提高所选存储器的通道的电压电平接近其目标值时,选择的存储器单元的偏置被改变为慢编程 细胞。 本发明的一个主要方面引入一个与可读取/写入电路相关联的锁存器,该读取/写入电路可以沿着相应的位线连接到每个选定的存储器单元,以便在该较低级别存储验证结果。