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91. 发明申请

US20080277786A1 Semiconductor package substrate 审中-公开
标题翻译：半导体封装基板
公开(公告)号：US20080277786A1
公开(公告)日：2008-11-13
申请号：US12156874
申请日：2008-06-05
申请人： Chun-Lung Chen , Yu-Po Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
发明人： Chun-Lung Chen , Yu-Po Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
IPC分类号： H01L23/48
CPC分类号： H05K1/115 , H01L23/3677 , H01L23/49822 , H01L24/16 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0206 , H05K1/112 , H05K2201/09627 , H05K2201/0979 , H05K2201/10674 , H01L2224/0401
摘要： A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate.
摘要翻译：半导体封装基板包括具有彼此相对的上表面和下表面的主体，形成在主体中的多个电路层，形成在主体的上表面上的多个焊盘，以及多个焊球衬垫形成在身体的下表面上。每个焊盘通过设置在电路层之间的电路层和导电结构电连接到焊球之一，其中电路层和导电结构被配置为以扇出方式向外扩展，以便提供电路层之间的距离更靠近主体的下表面的空间更多，使得焊料焊盘 - 焊球焊盘电连接的一部分可以包括形成在该空间中的多个平行连接的导电结构，从而增强导热通道和效果的散热而不必在基板的表面上设置更多的焊盘。

92. 发明申请

US20080224289A1 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

93. 发明申请

US20080150128A1 Heat dissipating chip structure and fabrication method thereof and package having the same 审中-公开
标题翻译：散热芯片结构及其制造方法及其封装
公开(公告)号：US20080150128A1
公开(公告)日：2008-06-26
申请号：US12004779
申请日：2007-12-21
申请人： Liang-Yi Hung , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Liang-Yi Hung , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/34 , H01L21/02
CPC分类号： H01L23/42 , H01L23/3128 , H01L23/36 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/0401 , H01L2224/16225 , H01L2224/16227 , H01L2224/29101 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/838 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/15311 , H01L2924/16152 , H01L2924/3011 , H01L2924/00 , H01L2924/3512
摘要： A heat dissipating chip structure and a fabrication method thereof and a package having the same are provided. The fabrication method mainly includes: forming a metal layer on an non-active surface of a wafer having a plurality of chips with the metal layer thereof providing a better solder bonding with a thermal interface material at positions corresponding to centers of each chips, and not being disposed on the cutting paths between the chips to prevent crack and peel off during the cutting. Further, when the chips are subsequently mounted on a chip carrier and further attached to a heat dissipating sheet with another metal layer on a surface thereof with the thermal interface material (TIM), with different surface areas of the metal layers formed on the heat dissipating sheet and the chip, an inward and downward force is generated in the TIM to limit an wetting area.
摘要翻译：散热芯片结构及其制造方法以及具有该散热芯片的封装。该制造方法主要包括：在具有多个芯片的晶片的非活性表面上形成金属层，其金属层与对应于每个芯片的中心的位置处的热界面材料提供更好的焊接，而不是设置在切屑之间的切割路径上，以防止切割期间的裂纹和剥离。此外，当芯片随后安装在芯片载体上并且进一步连接到具有热界面材料（TIM）的表面上的另一金属层的散热片时，在散热片上形成的金属层的不同表面积片材和芯片，TIM中产生向内和向下的力以限制润湿区域。

94. 发明申请

US20080088011A1 Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof 有权
标题翻译：可堆叠半导体器件的半导体封装及其制造方法
公开(公告)号：US20080088011A1
公开(公告)日：2008-04-17
申请号：US11974441
申请日：2007-10-12
申请人： Han-Ping Hu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Han-Ping Hu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/49 , H01L21/58
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/16151 , H01L2924/16195 , H01L2924/18161 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.
摘要翻译：提供半导体器件可堆叠的半导体封装件及其制造方法。该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电连接上层电路板，形成堆叠结构。

95. 发明授权

US07205642B2 Semiconductor package and method for fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US07205642B2
公开(公告)日：2007-04-17
申请号：US10972200
申请日：2004-10-22
申请人： Yu-Po Wang , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Yu-Po Wang , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/495
CPC分类号： H01L23/49822 , H01L21/561 , H01L23/13 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/484 , H01L2224/48599 , H01L2224/73215 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.
摘要翻译：提出了一种半导体封装及其制造方法。提供了具有形成在第一和第二电路层之间的第一电路层，第二电路层和芯层的衬底。在第二电路层上形成至少一个第二开口。在对应于第二开口的第一电路层上形成至少一个第一开口。在芯层中形成与第一电路层上的接合指状对应的多个指孔。在芯层中形成通孔，并与第一和第二开口连通。至少一个芯片安装在第一电路层上并且覆盖第一开口，其有源表面暴露于第一开口。形成密封剂以填充第一和第二开口和通孔并封装芯片。

96. 发明授权

US07074645B2 Fabrication method of semiconductor package with heat sink 有权
标题翻译：具有散热片的半导体封装的制造方法
公开(公告)号：US07074645B2
公开(公告)日：2006-07-11
申请号：US11013980
申请日：2004-12-15
申请人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/32 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/01028 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant. This allows the molding resin remained on the interface layer to be easily removed after completing the molding process, while delamination can be prevented from occurrence between the heat sink or the chip and the encapsulant, and also the chip can be prevented from cracking due to clamping force generated during molding.
摘要翻译：提出了具有散热器的半导体封装，其中芯片的第一表面附着到芯片载体上，而芯片的第二表面通过粘合剂附接到散热器，从而允许芯片产生的热量被传输到散热器此外，在成型工艺中，使用模塑树脂形成用于封装芯片的密封剂，同时连接到散热器的顶表面的顶表面和侧表面暴露于密封剂的外部，即热量水槽只有其底表面与密封剂结合。这使得所产生的热量通过散热器直接耗散到大气中。此外，散热器的顶表面涂覆有界面层，而界面层和模制树脂之间的粘合力小于散热器和密封剂之间的粘合。这允许在完成模制过程之后容易地去除界面层上的模塑树脂，同时可以防止散热片或芯片与密封剂之间发生分层，并且还可以防止芯片由于夹紧而开裂成型时产生的力。

97. 发明授权

US06963135B2 Semiconductor package for memory chips 失效
标题翻译：用于存储芯片的半导体封装
公开(公告)号：US06963135B2
公开(公告)日：2005-11-08
申请号：US10816339
申请日：2004-03-31
申请人： Cheng-Chian Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai
发明人： Cheng-Chian Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai
IPC分类号： G11C5/04 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/10 , H01L23/34
CPC分类号： H01L23/3121 , G11C5/04 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.
摘要翻译：半导体封装包括两个基板，每个基板具有多个电连接焊盘，安装在每个基板上的至少一个芯片，形成在每个基板上的封装体，用于封装芯片;以及盖，用于接收基板和芯片其中。芯片电连接到电连接焊盘。电连接垫从盖子露出并位于相同的表面上或相对布置。基板和盖子基本上具有矩形形状，每个基板的较长边与盖的较长边垂直。半导体封装结合有多个芯片以提高其性能和存储器容量，并且衬底小于现有技术中的衬底，因此制造更具成本效益。

98. 发明申请

US20050202590A1 Wafer level semiconductor package with build-up layer and method for fabricating the same 有权
标题翻译：具有积层的晶片级半导体封装及其制造方法
公开(公告)号：US20050202590A1
公开(公告)日：2005-09-15
申请号：US10846460
申请日：2004-05-14
申请人： Chien-Ping Huang , Cheng-Hsu Hsiao , Chih-Ming Huang
发明人： Chien-Ping Huang , Cheng-Hsu Hsiao , Chih-Ming Huang
IPC分类号： H01L21/44
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
摘要翻译：提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料，形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接到外部设备。通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。还提供了一种用于制造晶片级半导体封装的方法。

99. 发明申请

US20050095875A1 Fabrication method of semiconductor package with heat sink 有权
标题翻译：具有散热片的半导体封装的制造方法
公开(公告)号：US20050095875A1
公开(公告)日：2005-05-05
申请号：US11013980
申请日：2004-12-15
申请人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
IPC分类号： H01L21/56 , H01L23/31 , H01L23/433 , H01L23/34
CPC分类号： H01L24/32 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/01028 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor package with a heat sink is proposed, in which a chip has its first surface attached to a chip carrier, while a second surface of the chip is attached to a heat sink through an adhesive, allowing heat generated by the chip to be transmitted to the heat sink. Moreover, in a molding process, a molding resin is used to form an encapsulant for encapsulating the chip, while a top surface and side surfaces connected to the top surface of the heat sink are exposed to outside of the encapsulant, that is, the heat sink merely has its bottom surface bonded to the encapsulant. This makes the generated heat directly dissipated to the atmosphere through the heat sink. Furthermore, the top surface of the heat sink is coated with an interface layer, while adhesion between the interface layer and the molding resin is smaller than that between the heat sink and the encapsulant. This allows the molding resin remained on the interface layer to be easily removed after completing the molding process, while delamination can be prevented from occurrence between the heat sink or the chip and the encapsulant, and also the chip can be prevented from cracking due to clamping force generated during molding.
摘要翻译：提出了具有散热器的半导体封装，其中芯片的第一表面附着到芯片载体上，而芯片的第二表面通过粘合剂附接到散热器，从而允许芯片产生的热量被传输到散热器此外，在成型工艺中，使用模塑树脂形成用于封装芯片的密封剂，同时连接到散热器的顶表面的顶表面和侧表面暴露于密封剂的外部，即热量水槽只有其底表面与密封剂结合。这使得所产生的热量通过散热器直接耗散到大气中。此外，散热器的顶表面涂覆有界面层，而界面层和模制树脂之间的粘合力小于散热器和密封剂之间的粘合。这允许在完成模制过程之后容易地去除界面层上的模塑树脂，同时可以防止散热片或芯片与密封剂之间发生分层，并且还可以防止芯片由于夹紧而开裂成型时产生的力。

100. 外观设计

USD493799S1 Digital memory card 失效
标题翻译：数码存储卡
公开(公告)号：USD493799S1
公开(公告)日：2004-08-03
申请号：US29195995
申请日：2003-12-18
申请人： Cheng-Chia Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai
设计人： Cheng-Chia Chiang , Chih-Ming Huang , Chin-Huang Chang , Cheng-Hsu Hsiao , Min-Nan Tsai

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