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91. 发明授权

US06562684B1 Methods of forming dielectric materials 失效
标题翻译：形成电介质材料的方法
公开(公告)号：US06562684B1
公开(公告)日：2003-05-13
申请号：US09651818
申请日：2000-08-30
申请人： Behnam Moradi , Er-Xuan Ping , Lingyi A. Zheng , John Packard
发明人： Behnam Moradi , Er-Xuan Ping , Lingyi A. Zheng , John Packard
IPC分类号： H01L21336
CPC分类号： H01L21/02326 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/3144 , H01L28/40 , H01L28/84 , Y10S438/964
摘要： The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure. The structure includes a first capacitor electrode comprising a rugged polysilicon layer, a nitrogen-comprising layer on the rugged polysilicon layer, and a second capacitor electrode. The nitrogen-comprising layer is between the first and second capacitor electrodes.
摘要翻译：本发明包括形成电介质材料的方法。在坚固的多晶硅衬底的至少一些表面上形成含氮层以形成介电材料的第一部分。在形成含氮层之后，至少一些基底用NO和N 2 O中的一种或两种进行干式氧化以形成介电材料的第二部分。本发明还包括形成电容器的方法。在衬底上形成一层坚固的硅，并且在坚固的硅层上形成含氮层。一些粗糙的硅通过含氮层露出。在形成含氮层之后，暴露的粗糙硅中的至少一些经受具有NO和N 2 O中的一种或两种的干燥氧化条件。随后，在含氮层上形成导电材料层。另外，本发明包括电容器结构。该结构包括第一电容器电极，其包括坚固的多晶硅层，在凹凸多晶硅层上的含氮层和第二电容器电极。含氮层位于第一和第二电容器电极之间。

92. 发明授权

US06518611B1 Capacitor array structure for semiconductor devices 失效
标题翻译：半导体器件的电容阵列结构
公开(公告)号：US06518611B1
公开(公告)日：2003-02-11
申请号：US09698887
申请日：2000-10-27
申请人： Er-Xuan Ping
发明人： Er-Xuan Ping
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： Exemplary embodiments of the present invention teach a structure and process for forming an array of storage capacitors by forming a first set of individual storage node plates, forming alternating storage node pillars, forming a second set of individual storage node plates, forming a cell dielectric material on individual storage node plates, and forming a second capacitor plate over the first and second sets of individual storage node plates. The resulting structure comprises generally parallel running conductive word lines, a first set of individual storage node plates, storage node pillars alternating with individual storage node plates of the first set of individual storage node plates, a second set of individual storage node plates, a cell dielectric material on the first and second sets of individual storage node plates, and a second capacitor plate overlying the first and second sets of individual storage node plates.
摘要翻译：本发明的示例性实施例教导了通过形成第一组单独存储节点板来形成存储电容器阵列的结构和工艺，形成交替存储节点柱，形成第二组单独存储节点板，形成单元电介质材料并且在第一和第二组单独的存储节点板上形成第二电容器板。所得到的结构包括大致平行的运行导电字线，第一组单独的存储节点板，与第一组单独存储节点板的各个存储节点板交替的存储节点柱，第二组单独存储节点板，单元电介质材料在第一和第二组单独存储节点板上，以及第二电容器板，覆盖第一组和第二组单独的存储节点板。

93. 发明授权

US06500744B2 Methods of forming DRAM assemblies, transistor devices, and openings in substrates 有权
标题翻译：在基板中形成DRAM组件，晶体管器件和开口的方法
公开(公告)号：US06500744B2
公开(公告)日：2002-12-31
申请号：US09389670
申请日：1999-09-02
申请人： Fernando Gonzalez , Er-Xuan Ping
发明人： Fernando Gonzalez , Er-Xuan Ping
IPC分类号： H01L213205
CPC分类号： H01L21/763 , H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L27/10876
摘要： The invention encompasses a method of forming an opening in a substrate. A first expanse of a first material is formed over the substrate, and such expanse comprises a sidewall edge. A second material is formed along the sidewall edge, and subsequently a second expanse of the first material is formed over the substrate and separated from the first expanse by the second material. The first and second expanses together define a mask. The second material is removed with an etch selective for the second material relative to the first material to form an opening extending through the mask. The substrate is etched through the opening in the mask to extend the opening into the substrate. In a particular embodiment of the invention, the opening is filled with insulative material to form a trenched isolation region. In another embodiment of the invention, the opening is filled with a conductive material to form a transistor gate.
摘要翻译：本发明包括在衬底中形成开口的方法。在衬底上形成第一材料的第一层，并且这种膨胀层包括侧壁边缘。第二材料沿着侧壁边缘形成，随后第一材料的第二层被形成在衬底之上，并且通过第二材料与第一扩散层分离。第一个和第二个扩展在一起定义一个掩码。用相对于第一材料的第二材料选择性地蚀刻第二材料以形成延伸穿过掩模的开口。通过掩模中的开口蚀刻衬底以将开口延伸到衬底中。在本发明的一个具体实施例中，开口填充有绝缘材料以形成沟槽隔离区域。在本发明的另一个实施例中，开口填充有导电材料以形成晶体管栅极。

94. 发明授权

US06458699B1 Methods of forming a contact to a substrate 有权
标题翻译：与基材形成接触的方法
公开(公告)号：US06458699B1
公开(公告)日：2002-10-01
申请号：US09843116
申请日：2001-04-24
申请人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
发明人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
IPC分类号： H01L2144
CPC分类号： H01L29/41783 , C23C16/04 , C23C16/24 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L29/41775 , H01L29/7834
摘要： A method of forming a contact to a substrate includes forming insulating material comprising a substantially amorphous outer surface over a substrate node location. A contact opening is etched through the insulating material over the node location. The node location comprises an outwardly exposed substantially crystalline metal silicide surface. The substrate with outwardly exposed substantially crystalline metal silicide node location surface is provided within a chemical vapor deposition reactor. A gaseous precursor including silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed substantially crystalline metal silicide node location surface and not on the insulating material.
摘要翻译：形成与衬底的接触的方法包括形成在衬底节点位置上包括基本无定形的外表面的绝缘材料。通过节点位置处的绝缘材料蚀刻接触开口。节点位置包括向外暴露的基本上结晶的金属硅化物表面。具有向外暴露的基本上结晶的金属硅化物结点位置表面的衬底设置在化学气相沉积反应器内。包括硅的气体前体在有效地基本上选择性地在多晶硅上沉积在外露的基本上结晶的金属硅化物结点位置表面而不是绝缘材料上的条件下被供给到化学气相沉积反应器。

95. 发明授权

US06444590B2 Semiconductor processing methods, methods of forming hemispherical grain polysilicon, methods of forming capacitors, and methods of forming wordlines 失效
标题翻译：半导体加工方法，形成半球形晶粒多晶硅的方法，形成电容器的方法以及形成字线的方法
公开(公告)号：US06444590B2
公开(公告)日：2002-09-03
申请号：US09751213
申请日：2000-12-29
申请人： Er-Xuan Ping , Li Li
发明人： Er-Xuan Ping , Li Li
IPC分类号： H01L21302
CPC分类号： H01L21/02049 , C09K13/06 , H01L21/02063 , H01L21/02068 , H01L28/84
摘要： In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.
摘要翻译：一方面，本发明包括半导体处理方法，其包括使表面与包含至少一种含氟物质的液体溶液和至少约40℃的温度接触。另一方面，本发明包括钝化含硅层包括使该层与包含氟化氢的液体溶液接触并且至少约40℃的温度。在另一方面，本发明包括形成半球形晶粒多晶硅的方法，包括：a）形成包括基本上非晶硅; b）使包含基本上非晶硅的层与包含含氟物质的液体溶液和至少约40℃的温度接触; c）将包含基本上非晶硅的层接种; 以及d）退火所述接种层以将所述接种层的至少一部分转化为半球形晶粒多晶硅。

96. 发明授权

US06441494B2 Microelectronic contacts 有权
标题翻译：微电子触点
公开(公告)号：US06441494B2
公开(公告)日：2002-08-27
申请号：US09834192
申请日：2001-04-12
申请人： Yin Huang , Er-Xuan Ping
发明人： Yin Huang , Er-Xuan Ping
IPC分类号： H01L2352
CPC分类号： H01L21/76838 , H01L21/76805 , H01L21/76814 , H01L21/76816 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method for producing reliable contacts in microelectronic devices and contacts produced thereby are provided. In one embodiment of the invention, a first conductive layer is formed over a first dielectric layer. The first conductive layer contains a pattern etched therein. A second dielectric layer is deposited over the first conductive layer and a via is etched therein over the pattern, thus exposing a portion of the pattern and the first conductive layer. The structure is then further etched to remove a portion of the first dielectric layer using the exposed portions of the first conductive layer as a mask. The structure is then subject to an isotropic etch to create undercuts in the first dielectric layer underneath the exposed portions of the first conductive layer. A conductive material can then be deposited into the via to fill the undercut, thus contacting the first conductive material on the exposed top, sides, and underside of the layer to produce a highly reliable contact. This technique is also adapted to create vias that are used to connect three or more conductive layers.
摘要翻译：提供了一种用于在微电子器件中产生可靠的触点的方法和由此产生的触点。在本发明的一个实施例中，在第一电介质层上形成第一导电层。第一导电层包含蚀刻在其中的图案。在第一导电层上沉积第二电介质层，并且在图案上蚀刻通孔，从而暴露图案的一部分和第一导电层。然后使用第一导电层的暴露部分作为掩模，进一步蚀刻该结构以去除第一介电层的一部分。然后将该结构进行各向同性蚀刻，以在第一导电层的暴露部分下面的第一介电层中产生底切。然后可以将导电材料沉积到通孔中以填充底切，从而使第一导电材料接触在该层的暴露的顶部，侧面和下侧，以产生高度可靠的接触。该技术还适于产生用于连接三个或更多个导电层的通孔。

97. 发明授权

US06350648B1 Formation of conductive rugged silicon 失效
标题翻译：形成导电坚固的硅
公开(公告)号：US06350648B1
公开(公告)日：2002-02-26
申请号：US09503669
申请日：2000-02-14
申请人： Er-Xuan Ping , Randhir Thakur
发明人： Er-Xuan Ping , Randhir Thakur
IPC分类号： C23C1624
CPC分类号： H01L28/84 , C23C16/24 , C23C16/56 , Y10S438/964
摘要： The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of doped amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the amorphous silicon layer into hemispherical grain silicon by annealing the amorphous silicon layer at substantially the deposition temperature while varying pressure. In another aspect, the methods involve forming a discontinuous first layer of doped silicon on a substrate; forming a second layer of amorphous silicon on the first layer of doped silicon and the substrate not covered by the first layer of doped silicon; and annealing the first and second layers. In yet another aspect, the methods involve forming a discontinuous first layer of silicon on a substrate and forming a second conformal layer of doped amorphous silicon on the first layer of doped silicon.
摘要翻译：本发明提供了形成原位掺杂的坚固硅和掺入导电坚固硅的半导体器件的方法。在一个方面，所述方法包括在基本上恒定的沉积温度下在衬底上形成掺杂的非晶硅层; 以及通过在改变压力的同时基本上淀积温度退火所述非晶硅层，将所述非晶硅层转化为半球形晶粒硅。在另一方面，所述方法包括在衬底上形成不连续的第一掺杂硅层; 在所述第一掺杂硅层上形成第二非晶硅层，并且所述衬底未被所述第一掺杂硅层覆盖; 并退火第一和第二层。在另一方面，所述方法包括在衬底上形成不连续的第一硅层，并在第一掺杂硅层上形成掺杂非晶硅的第二共形层。

98. 发明授权

US06169037A Semiconductor processing methods 失效
标题翻译：半导体加工方法
公开(公告)号：US06169037A
公开(公告)日：2001-01-02
申请号：US09476182
申请日：2000-01-03
申请人： Er-Xuan Ping , Li Li
发明人： Er-Xuan Ping , Li Li
IPC分类号： H01L21302
CPC分类号： H01L21/02049 , C09K13/06 , H01L21/02063 , H01L21/02068 , H01L28/84
摘要： In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.
摘要翻译：一方面，本发明包括半导体处理方法，其包括使表面与包含至少一种含氟物质的液体溶液和至少约40℃的温度接触。另一方面，本发明包括钝化含硅层包括使该层与包含氟化氢的液体溶液接触并且至少约40℃的温度。在另一方面，本发明包括形成半球形晶粒多晶硅的方法，包括：a）形成包括基本上非晶硅; b）使包含基本上非晶硅的层与包含含氟物质的液体溶液和至少约40℃的温度接触; c）将包含基本上非晶硅的层接种; 以及d）退火所述接种层以将所述接种层的至少一部分转化为半球形晶粒多晶硅。

99. 发明授权

US6159852A Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor 失效
标题翻译：沉积多晶硅的方法，制造场效应晶体管的方法，与衬底形成接触的方法，形成电容器的方法
公开(公告)号：US6159852A
公开(公告)日：2000-12-12
申请号：US23239
申请日：1998-02-13
申请人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
发明人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
IPC分类号： C23C16/04 , C23C16/24 , H01L21/285 , H01L21/768 , H01L29/417 , H01L29/78 , H01L21/4763
CPC分类号： H01L29/41783 , C23C16/04 , C23C16/24 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L29/41775 , H01L29/7834
摘要： In a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on amorphous material, and forming elevated source/drains on the doped source/drain regions. In another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material.
摘要翻译：在沉积多晶硅的方法中包括在化学气相沉积反应器内提供衬底，其中衬底具有暴露的基本上结晶的区域和暴露的基本非晶区域。包含硅的气体前体在有效选择性地在结晶区域而非非晶区域上沉积多晶硅的条件下进料至化学气相沉积反应器。在另一方面，在衬底上制造场效应晶体管的方法包括形成栅极介电层和半导体材料上的栅极。包含硅的气体前体在有效基本上选择性地在源极/漏极区域上而不是无定形材料上沉积多晶硅并且在掺杂源极/漏极区域上形成升高的源极/漏极的条件下被馈送到化学气相沉积反应器。另一方面，公开了一种形成与基板的接触的方法。接触开口在最终包括向外暴露的基本上结晶的表面的节点位置上通过非晶绝缘材料蚀刻。在化学气相沉积反应器内，在有效选择性地将多晶硅沉积在外露的晶体结点位置表面而不是在绝缘材料上的条件下提供了包含硅的气态前体。

100. 发明授权

US6124164A Method of making integrated capacitor incorporating high K dielectric 有权
标题翻译：制造集成电容器的高K电介质的方法
公开(公告)号：US6124164A
公开(公告)日：2000-09-26
申请号：US156545
申请日：1998-09-17
申请人： Husam N. Al-Shareef , Er-Xuan Ping
发明人： Husam N. Al-Shareef , Er-Xuan Ping
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8249
CPC分类号： H01L28/55 , H01L28/91 , H01L27/10852 , H01L28/82
摘要： An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.
摘要翻译：提供了一种集成电容器，其包括高介电常数材料。在公开的方法中，高k电容器电介质形成为保护层上方的容器形状。在形成电介质之后，形成表示存储单元的存储和参考电极的内部和外部电极。接触件通过保护层从存储电极层分别制成，该电极层将电介质的内表面排列到下面的多晶硅插塞。接触可以是在存储电极层的内部衬里的薄层，或者可以完全填充容器电容器。在后一种情况下，接触可以形成存储电极的一部分并有助于电池的电容。因此，可以在电极之前形成挥发性介电材料，避免电极和下面的多晶硅插塞的氧化，同时还通过从高介电常数材料的扩散减少氧耗尽。

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