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    • 93. 发明授权
    • Dummy clock control method and apparatus for a sequential I/O device
    • 用于顺序I / O设备的虚拟时钟控制方法和装置
    • US06404938B1
    • 2002-06-11
    • US09233214
    • 1999-01-20
    • Chun-Tsai ChienChun-Liang Lin
    • Chun-Tsai ChienChun-Liang Lin
    • G06K700
    • G06K7/1092H04N1/0402H04N2201/0454
    • A method and apparatus for speeding up the reading speed of a sequential I/O device, such as a Charge Coupled Device, is disclosed. The method involves in providing normal clocks for reading selected pixels and dummy clocks for reading unselected pixels. Since dummy clocks are faster than normal clocks, therefore the total time for processing the document can be less than using clocks of uniform speed. The apparatus of the invention comprises: a clock control device for generating two transfer pulses &phgr;1 and &phgr;2 in response to a clock cycle. The transfer pulses &phgr;1 and &phgr;2 are input to a sequential I/O device. The signal charge generated from the sequential I/O device will then output to an AND converter to be converted into digital signals. If the digital signals are marked, they will be latched. If not, they will simply be ignored.
    • 公开了一种用于加速诸如电荷耦合装置的顺序I / O装置的读取速度的方法和装置。 该方法涉及提供用于读取所选像素的正常时钟和用于读取未选择像素的虚拟时钟。 由于虚拟时钟比正常时钟快,因此处理文档的总时间可能小于使用均匀速度的时钟。 本发明的装置包括:时钟控制装置,用于响应于时钟周期产生两个传送脉冲phi1和phi2。 传送脉冲phi1和phi2被输入到顺序I / O设备。 然后,从顺序I / O设备产生的信号电荷将输出到一个AND转换器,以转换成数字信号。 如果数字信号被标记,它们将被锁定。 如果没有,他们将被忽略。