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91. 发明授权

US07960795B2 Partially and fully silicided gate stacks 有权
标题翻译：部分和完全硅化栅极堆叠
公开(公告)号：US07960795B2
公开(公告)日：2011-06-14
申请号：US12782388
申请日：2010-05-18
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L21/70 , H01L21/311
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

92. 发明申请

US20110133169A1 Gate-All-Around Nanowire Tunnel Field Effect Transistors 有权
标题翻译：门 - 全能纳米线隧道场效应晶体管
公开(公告)号：US20110133169A1
公开(公告)日：2011-06-09
申请号：US12630942
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78 , H01L29/08
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/66469 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译：一种形成纳米线隧道场效应晶体管（FET）器件的方法包括：在半导体衬底上形成由第一和第二衬垫区域悬挂的纳米线，纳米线包括芯部分和电介质层，在该部分的一部分周围形成栅极结构电介质层，在从所述栅极结构延伸的所述纳米线的一部分周围形成第一间隔物，在所述纳米线的第一部分中注入离子，将所述离子注入到所述纳米线的第二部分的介电层中，从所述第二部分去除所述电介质层去除所述暴露的纳米线的第二部分的核心部分以形成空腔，并且从所述纳米线和所述第二焊盘区域的暴露的横截面外延生长所述空腔中的掺杂半导体材料，以将所述暴露的横截面纳米线到第二垫区域。

93. 发明申请

US20110133166A1 NANOWIRE FET HAVING INDUCED RADIAL STRAIN 有权
标题翻译：具有诱导径向应变的纳米效应管
公开(公告)号：US20110133166A1
公开(公告)日：2011-06-09
申请号：US12631218
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Conal E. Murray , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Conal E. Murray , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/336 , H01L21/66
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/4908 , H01L29/66439 , H01L29/66469 , H01L29/66772 , H01L29/775 , H01L29/7845 , H01L29/78696
摘要： A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.
摘要翻译：提供了一种器件，并且包括连接第一和第二绝缘体上硅（SOI）焊盘的纳米线和包括围绕纳米线的栅极导体的栅极和围绕栅极导体的全硅化物材料以径向应变纳米线。

94. 发明申请

US20110133164A1 Omega Shaped Nanowire Field Effect Transistors 有权
标题翻译：欧米茄形纳米线场效应晶体管
公开(公告)号：US20110133164A1
公开(公告)日：2011-06-09
申请号：US12631205
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/845 , H01L27/1211 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/66628 , H01L29/66772 , H01L29/78645 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的第一部分上形成第一栅极结构，形成与第一栅极结构的侧壁相邻的第一保护隔离层，纳米线的部分从第一栅极结构延伸，去除未被第一间隔物保护的纳米线的暴露部分，并且在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成第一源极区域和第一漏极区域。

95. 发明申请

US20110133162A1 Gate-All-Around Nanowire Field Effect Transistors 有权
标题翻译：门 - 全能纳米线场效应晶体管
公开(公告)号：US20110133162A1
公开(公告)日：2011-06-09
申请号：US12631199
申请日：2009-12-04
申请人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Josephine B. Chang , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/66772 , B82Y10/00 , H01L21/845 , H01L27/1211 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/66628 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
摘要翻译：一种用于形成纳米线场效应晶体管（FET）器件的方法，该方法包括在半导体衬底上形成悬浮的纳米线，在纳米线的一部分周围形成栅极结构，形成邻近栅极的侧壁和周围部分的保护隔离层的纳米线从栅极延伸，去除未被间隔物结构保护的纳米线的暴露部分，以及在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成源极区域和漏极区域。

96. 发明授权

US07948307B2 Dual dielectric tri-gate field effect transistor 有权
标题翻译：双介质三栅场效应晶体管
公开(公告)号：US07948307B2
公开(公告)日：2011-05-24
申请号：US12561880
申请日：2009-09-17
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L25/00
CPC分类号： H01L29/66795 , H01L21/84 , H01L27/1203 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt1, and the gate electrode and the second dielectric layer form a third gate having a threshold voltage Vt2 different than Vt1.
摘要翻译：公开了双电介质三栅场效应晶体管，制造双电介质三栅场效应晶体管的方法，以及操作双电介质三栅效应晶体管的方法。在一个实施例中，双电介质三栅晶体管包括衬底，衬底上的绝缘层和至少一个半导体鳍片。具有第一介电常数的第一电介质在翅片的侧壁上延伸，并且金属层在第一电介质上延伸，并且具有第二介电常数的第二电介质位于散热片的顶表面上。栅电极在鳍片和第一和第二电介质上延伸。栅电极和第一电介质层形成具有阈值电压Vt1的第一栅极和第二栅极，栅电极和第二电介质层形成具有不同于Vt1的阈值电压Vt2的第三栅极。

97. 发明申请

US20110115032A1 HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER 有权
标题翻译：具有L形门盖的高K /金属栅极晶体管
公开(公告)号：US20110115032A1
公开(公告)日：2011-05-19
申请号：US12551292
申请日：2009-11-18
申请人： RENEE T. MO , Wesley C. Natzle , Vijay Narayanan , Jeffrey W. Sleight
发明人： RENEE T. MO , Wesley C. Natzle , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.
摘要翻译：提供晶体管，其包括具有源极区和漏极区的硅层，设置在源极区和漏极区之间的硅层上的栅极堆叠，设置在栅极堆叠的侧壁上的L形栅极封装层，以及设置在栅极封装层的水平部分上方并且与栅极封装层的垂直部分相邻的间隔物。栅堆叠具有第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。栅极封装层具有覆盖栅极堆叠的第一，第二和第三层的侧壁的垂直部分和覆盖与栅极叠层相邻的硅层的一部分的水平部分。

98. 发明申请

US20110108804A1 Maskless Process for Suspending and Thinning Nanowires 失效
标题翻译：用于悬浮和稀释纳米线的无掩模工艺
公开(公告)号：US20110108804A1
公开(公告)日：2011-05-12
申请号：US13006833
申请日：2011-01-14
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

99. 发明申请

US20110073958A1 ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL 有权
标题翻译：不对称硅绝缘体SRAM单元
公开(公告)号：US20110073958A1
公开(公告)日：2011-03-31
申请号：US12566717
申请日：2009-09-25
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： H01L27/11 , H01L21/8234
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11 , H01L27/1203
摘要： A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.
摘要翻译：具有N个晶体管的存储单元，其包括至少一对存取晶体管，一对下拉晶体管和一对上拉晶体管，以形成存储单元，其中N是至少等于6的整数，其中每个的存取晶体管，并且每个下拉晶体管是n型或p型晶体管中的相同的一个，并且每个上拉晶体管是n型或p型晶体管中的另一个，其中所述一对下拉晶体管和所述一对上拉晶体管中的至少一个是不对称的。

100. 发明申请

US20100327376A1 Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same 有权
标题翻译：具有硅侧壁的金属高K晶体管用于减少寄生电容，以及制造相同的工艺
公开(公告)号：US20100327376A1
公开(公告)日：2010-12-30
申请号：US12880478
申请日：2010-09-13
申请人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
发明人： Leland Chang , Jeffrey W. Sleight , Isaac Lauer , Renee T. Mo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/26586 , H01L21/28105 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656
摘要： A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.
摘要翻译：一种方法形成金属高介电常数（MHK）晶体管，包括：提供设置在衬底上的MHK堆叠，MHK堆叠包括第一层高介电常数材料，第二覆盖层和第三覆盖层; 选择性地仅去除第二层和第三层，而不去除第一层，以形成MHK栅极结构的直立部分; 在MHK门结构的直立部分的侧壁上形成第一侧壁层; 在所述第一侧壁层的侧壁上形成第二侧壁层; 去除第一层的一部分以形成暴露的表面; 在所述第二侧壁层上并在所述第一层之上形成偏移间隔层，以及在所述第一和第二侧壁层的底部延伸部中形成并且在所述MHK栅极结构的一部分但不是全部直立部分的下方延伸。

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