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91. 发明申请

US20070235835A1 Shallow trench isolation structure for semiconductor device 有权
标题翻译：用于半导体器件的浅沟槽隔离结构
公开(公告)号：US20070235835A1
公开(公告)日：2007-10-11
申请号：US11809519
申请日：2007-05-31
申请人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
发明人： Chih-Hsin Ko , Chung-Hu Ke , Chien-Chao Huang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L21/76232 , H01L21/823481 , H01L29/66636 , H01L29/7834
摘要： A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing by a gaseous ambient to reflow the edges of the trenches causing the edges to become rounded and overhang the trench. The filler material may be a dielectric. The transistors which are then formed in close proximity to the trenches may include source/drain regions formed in the rounded portion of the semiconductor substrate that overhangs the trench.
摘要翻译：半导体器件提供与隔离沟槽相邻的晶体管。该器件可以通过在半导体衬底中产生隔离沟槽，用填充材料填充沟槽，在沟槽的顶部边缘附近产生空隙，并通过气态环境进行退火以使沟槽的边缘回流，从而使边缘变圆; 突出沟槽。填充材料可以是电介质。然后形成在靠近沟槽的晶体管可以包括形成在半导体衬底的圆形部分中的突出于沟槽的源极/漏极区域。

92. 发明授权

US08785285B2 Semiconductor devices and methods of manufacture thereof 有权
公开(公告)号：US08785285B2
公开(公告)日：2014-07-22
申请号：US13415710
申请日：2012-03-08
申请人： Ji-Yin Tsai , Yao-Tsung Huang , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Ji-Yin Tsai , Yao-Tsung Huang , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/336
CPC分类号： H01L27/0886 , H01L29/45 , H01L29/66795 , H01L29/7848 , H01L29/7851
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

93. 发明授权

US08629012B2 Method for forming antimony-based FETs monolithically 有权
标题翻译：一体形成锑基FET的方法
公开(公告)号：US08629012B2
公开(公告)日：2014-01-14
申请号：US13595797
申请日：2012-08-27
申请人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Heng-Kuang Lin , Pei-Chin Chiu , Jen-Inn Chyi , Han-Chieh Ho , Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L21/338
CPC分类号： H01L29/205 , B82Y10/00 , H01L21/8252 , H01L27/085 , H01L27/0883 , H01L27/092 , H01L29/122 , H01L29/42316 , H01L29/42356 , H01L29/66462 , H01L29/7783
摘要： An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.
摘要翻译：集成电路结构包括基板和第一和第二多个III-V半导体层。所述第一多个III-V半导体层包括在所述衬底上的第一底部阻挡层; 在第一底部屏障上的第一通道层; 以及第一通道层上的第一顶部势垒。第一场效应晶体管（FET）包括第一沟道区，其包括第一沟道层的一部分。第二多个III-V半导体层在第一多个III-V半导体层之上，并且包括第二底部屏障; 在第二底部屏障上的第二通道层; 以及在第二通道层上的第二顶部阻挡层。第二FET包括第二沟道区，其包括第二沟道层的一部分。

94. 发明授权

US08609518B2 Re-growing source/drain regions from un-relaxed silicon layer 有权
标题翻译：从不放松的硅层再生长源极/漏极区域
公开(公告)号：US08609518B2
公开(公告)日：2013-12-17
申请号：US13189119
申请日：2011-07-22
申请人： Clement Hsingjen Wann , Chih-Hsin Ko , Yao-Tsung Huang , Cheng-Ying Huang
发明人： Clement Hsingjen Wann , Chih-Hsin Ko , Yao-Tsung Huang , Cheng-Ying Huang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.
摘要翻译：形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。在硅层上形成栅堆叠。硅层凹陷以形成邻近栅堆叠的凹陷。在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。

95. 发明授权

US08609517B2 MOCVD for growing III-V compound semiconductors on silicon substrates 有权
标题翻译：用于在硅衬底上生长III-V化合物半导体的MOCVD
公开(公告)号：US08609517B2
公开(公告)日：2013-12-17
申请号：US12814088
申请日：2010-06-11
申请人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
发明人： Clement Hsingjen Wann , Chih-Hsin Ko , Cheng-Hsien Wu
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/0262 , C30B25/105 , C30B25/186 , C30B29/40 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/76224
摘要： A device includes providing a silicon substrate; annealing the silicon substrate at a first temperature higher than about 900° C.; and lowering a temperature of the silicon substrate from the first temperature to a second temperature. A temperature lowering rate during the step of lowering the temperature is greater than about 1° C./second. A III-V compound semiconductor region is epitaxially grown on a surface of the silicon substrate using metal organic chemical vapor deposition (MOCVD).
摘要翻译：一种器件包括提供硅衬底; 在高于约900℃的第一温度下退火硅衬底; 以及将所述硅衬底的温度从所述第一温度降低到第二温度。在降低温度的步骤期间的降温速率大于约1℃/秒。使用金属有机化学气相沉积（MOCVD）在硅衬底的表面上外延生长III-V族化合物半导体区域。

96. 发明授权

US08486770B1 Method of forming CMOS FinFET device 有权
标题翻译： CMOS FinFET器件的形成方法
公开(公告)号：US08486770B1
公开(公告)日：2013-07-16
申请号：US13340937
申请日：2011-12-30
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/335
CPC分类号： H01L27/1211 , H01L21/823821 , H01L21/8258 , H01L21/845 , H01L29/1054 , H01L29/267
摘要： A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.
摘要翻译：公开了一种用于制造CMOS FinFET器件的CMOS FinFET器件和方法。示例性的CMOS FinFET器件包括包括第一区域和第二区域的衬底。 CMOS FinFET还包括布置在衬底上的翅片结构，其包括在第一区域中的第一鳍片和在第二区域中的第二鳍片。 CMOS FinFET还包括第一鳍片的第一部分，其包括与衬底相同的材料的材料，以及第一鳍片的第二部分，其包括沉积在第一鳍片的第一部分上的III-V半导体材料。 CMOS FinFET还包括第二鳍片的第一部分，其包括与衬底相同的材料，第二鳍片的第二部分包括沉积在第二鳍片的第一部分上的锗（Ge）材料。

97. 发明申请

US20130126985A1 (110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR SUBSTRATE 有权
标题翻译：（110）用于降低高K电介质和III-V族化合物半导体衬底之间的电荷密度的表面定向
公开(公告)号：US20130126985A1
公开(公告)日：2013-05-23
申请号：US13299529
申请日：2011-11-18
申请人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
发明人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/785 , H01L21/28264 , H01L21/3081 , H01L29/045 , H01L29/0649 , H01L29/20 , H01L29/452 , H01L29/4916 , H01L29/517 , H01L29/66522
摘要： A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
摘要翻译：公开了一种具有改进的器件性能的器件及其制造方法。示例性器件包括III-V族化合物半导体衬底，其包括具有（110）结晶取向的表面和设置在III-V族化合物半导体衬底上的栅叠层。栅极堆叠包括设置在具有（110）晶体取向的表面上的高k电介质层，以及设置在高k电介质层上的栅电极。

98. 发明授权

US08426890B2 Semiconductor device and manufacturing method with improved epitaxial quality of III-V compound on silicon surfaces 有权
标题翻译：具有提高硅表面III-V化合物外延质量的半导体器件和制造方法
公开(公告)号：US08426890B2
公开(公告)日：2013-04-23
申请号：US13461595
申请日：2012-05-01
申请人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L31/102
CPC分类号： H01L21/8258 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02538 , H01L21/02639 , H01L21/02667 , H01L21/02675
摘要： Stacking faults are reduced or eliminated by epitaxially growing a III-V compound semiconductor region in a trench followed by capping and annealing the region. The capping layer limits the escape of atoms from the region and enables the reduction or elimination of stacking faults along with the annealing.
摘要翻译：通过在沟槽中外延生长III-V族化合物半导体区域，然后对该区域进行封盖和退火，来减少或消除堆叠故障。封盖层限制了原子从该区域的逃逸，并且能够与退火一起减少或消除堆垛层错。

99. 发明申请

US20130020612A1 Re-growing Source/Drain Regions from Un-Relaxed Silicon Layer 有权
标题翻译：从不轻松的硅层重新增长源/排水区域
公开(公告)号：US20130020612A1
公开(公告)日：2013-01-24
申请号：US13189119
申请日：2011-07-22
申请人： Clement Hsingjen Wann , Chih-Hsin Ko , Yao-Tsung Huang , Cheng-Ying Huang
发明人： Clement Hsingjen Wann , Chih-Hsin Ko , Yao-Tsung Huang , Cheng-Ying Huang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.
摘要翻译：形成n型金属氧化物半导体（NMOS）场效应晶体管（FET）的方法包括形成硅锗层，并在硅锗层上形成硅层。在硅层上形成栅堆叠。硅层凹陷以形成邻近栅堆叠的凹陷。在凹部中外延生长含硅半导体区域以形成源极/漏极应力源，其中所述含硅半导体区域形成NMOS FET的源极/漏极区域。

100. 发明申请

US20120001239A1 Formation of III-V Based Devices on Semiconductor Substrates 有权
标题翻译：在半导体基板上形成基于III-V的器件
公开(公告)号：US20120001239A1
公开(公告)日：2012-01-05
申请号：US12827709
申请日：2010-06-30
申请人： Chih-Hsin Ko , Clement Hsingjen Wann
发明人： Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L27/085 , H01L29/20
CPC分类号： H01L29/785 , H01L29/66795
摘要： A device includes a semiconductor substrate, and insulation regions in the semiconductor substrate. Opposite sidewalls of the insulation regions have a spacing between about 70 nm and about 300 nm. A III-V compound semiconductor region is formed between the opposite sidewalls of the insulation regions.
摘要翻译：一种器件包括半导体衬底和半导体衬底中的绝缘区域。绝缘区域的相对侧壁的间隔为约70nm至约300nm。在绝缘区域的相对侧壁之间形成III-V族化合物半导体区域。

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