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91. 发明申请

US20130032950A1 Techniques for Interconnecting Stacked Dies Using Connection Sites 有权
标题翻译：使用连接站点互连堆叠模块的技术
公开(公告)号：US20130032950A1
公开(公告)日：2013-02-07
申请号：US13641680
申请日：2011-04-13
申请人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
发明人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外的核心电路。核心电路耦合到至少一个连接位置。

92. 发明申请

US20120184242A1 Methods and Systems for Enhancing Wireless Coverage 审中-公开
标题翻译：增强无线覆盖的方法和系统
公开(公告)号：US20120184242A1
公开(公告)日：2012-07-19
申请号：US13499194
申请日：2010-08-31
申请人： Adam H. Li , Ning Nicholas Chen , Ely Tsern , Michael Farmwald
发明人： Adam H. Li , Ning Nicholas Chen , Ely Tsern , Michael Farmwald
IPC分类号： H04W12/06 , H04W4/26
CPC分类号： H04W12/06 , H04L63/0815 , H04L63/0892 , H04W40/02 , H04W88/06
摘要： Described are methods, devices, and systems to provide enhanced wireless coverage for wireless mobile stations by facilitating centralized authentication for a variety of unrelated networks. The mobile stations can then access Internet and telephony resources via the various networks for improved coverage and bandwidth. Some embodiments support the extension of network coverage using wireless-access points that can be partitioned into multiple virtual access points, one associated with an enterprise and another with an overlay network that facilitates mobile communication over multiple networks. One physical access point can support an enterprise network using one virtual access point and the overlay network using another. Users unaffiliated with an enterprise can access the overlay network via the enterprise's physical access point without gaining access to the enterprise network.
摘要翻译：描述了通过促进各种不相关网络的集中认证来为无线移动站提供增强的无线覆盖的方法，设备和系统。然后，移动台可以经由各种网络访问因特网和电话资源，以改善覆盖和带宽。一些实施例支持使用可以被划分成多个虚拟接入点的无线接入点来扩展网络覆盖范围，一个与企业相关联，另一个具有促进多个网络上的移动通信的覆盖网络。一个物理接入点可以使用一个虚拟接入点和使用另一个的覆盖网络来支持企业网络。与企业无关的用户可以通过企业的物理接入点访问覆盖网络，无需访问企业网络。

93. 发明授权

US07592824B2 Method and apparatus for test and characterization of semiconductor components 有权
标题翻译：用于半导体元件测试和表征的方法和装置
公开(公告)号：US07592824B2
公开(公告)日：2009-09-22
申请号：US10768443
申请日：2004-01-30
申请人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
发明人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

94. 发明申请

US20090195350A1 Situationally Aware and Self-Configuring Electronic Data And Communication Device 有权
标题翻译：情境意识和自配电子数据和通信设备
公开(公告)号：US20090195350A1
公开(公告)日：2009-08-06
申请号：US12363397
申请日：2009-01-30
申请人： Ely Tsern , Dave Mooring
发明人： Ely Tsern , Dave Mooring
IPC分类号： G05B23/02 , G06F1/24 , G08B1/08 , H04M1/00
CPC分类号： G06F1/1694 , G01S19/42 , G06F1/1626 , G06F1/163 , G06F1/1632 , G06F1/1684 , G06F9/453
摘要： A self-configuring wearable electronic data and communication device comprising a self-contained module comprising means for self-configuring based on a user's activity and context an operational mode in a plurality of operational modes, wherein the self contained module further comprises intelligent situational awareness derived from at least one of pre-programmed criteria, a sensing ability, a user-specified lifestyle theme, a communication functionality, an accessory, and a user motion pattern. The self-contained module further comprises a display, a processor, a memory, and a battery, and is capable of configuring itself according to an accessory to which it is attached or connected.
摘要翻译：一种自配置的可穿戴电子数据和通信设备，包括自包含模块，其包括用于基于用户的活动和上下文的多个操作模式中的操作模式进行自配置的装置，其中所述自包含模块还包括导出的智能状态感知从预编程标准，感测能力，用户指定的生活方式主题，通信功能，附件和用户运动模式中的至少一个。独立模块还包括显示器，处理器，存储器和电池，并且能够根据其所附接或连接的附件来配置自身。

95. 发明授权

US07526597B2 Buffered memory having a control bus and dedicated data lines 失效
标题翻译：具有控制总线和专用数据线的缓冲存储器
公开(公告)号：US07526597B2
公开(公告)日：2009-04-28
申请号：US11868242
申请日：2007-10-05
申请人： Richard Perego , Fred Ware , Ely Tsern
发明人： Richard Perego , Fred Ware , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1806 , H05K1/181
摘要： A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.
摘要翻译：存储器系统架构/互连拓扑包括具有可配置宽度缓冲器件的可配置宽度缓冲模块。可配置宽度缓冲器设备耦合到可配置宽度存储器模块上的至少一个存储器件。可配置宽度缓冲器装置包括接口和可配置串行化电路，其能够改变在可配置宽度缓冲器装置的接口处使用的数据路径宽度或数量的接触访问至少一个存储器件。在本发明的另一个实施例中，提供了多路复用器/解复用器电路。状态存储器为可配置的宽度缓冲器提供数据宽度，并且SPD向存储器系统提供可配置的宽度缓冲器和/或模块功能。

96. 发明授权

US07464225B2 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 有权
标题翻译：存储器模块包括多个集成电路存储器件和矩阵拓扑中的多个缓冲器件
公开(公告)号：US07464225B2
公开(公告)日：2008-12-09
申请号：US11236401
申请日：2005-09-26
申请人： Ely Tsern
发明人： Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C11/4093 , G11C2029/4402 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/14 , H01L2924/15182 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.
摘要翻译：存储器模块包括多个信号路径，其从接收来自相关联的多个集成电路存储器件的数据的多个相应的集成电路缓冲器装置向存储器模块连接器接口提供数据。存储器模块形成耦合到各个集成电路缓冲器件的多个“数据片”或存储器模块数据总线的多个部分。每个集成电路缓冲器件还耦合到总线，该总线提供指定访问至少一个集成电路存储器件的控制信息。根据实施例，SPD设备存储关于存储器模块的配置信息的信息。在实施例中，至少一个集成电路缓冲器设备访问存储在SPD设备中的信息。在封装实施例中，封装容纳集成电路缓冲管芯和多个集成电路存储器管芯。

97. 发明申请

US20070247935A1 Clocked Memory System with Termination Component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US20070247935A1
公开(公告)日：2007-10-25
申请号：US11767983
申请日：2007-06-25
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

98. 发明申请

US20070070669A1 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 有权
标题翻译：存储器模块包括多个集成电路存储器件和矩阵拓扑中的多个缓冲器件
公开(公告)号：US20070070669A1
公开(公告)日：2007-03-29
申请号：US11236401
申请日：2005-09-26
申请人： Ely Tsern
发明人： Ely Tsern
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C11/4093 , G11C2029/4402 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/14 , H01L2924/15182 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.
摘要翻译：存储器模块包括多个信号路径，其从接收来自相关联的多个集成电路存储器件的数据的多个相应的集成电路缓冲器件向存储器模块连接器接口提供数据。存储器模块形成耦合到各个集成电路缓冲器件的多个“数据片”或存储器模块数据总线的多个部分。每个集成电路缓冲器件还耦合到总线，该总线提供指定访问至少一个集成电路存储器件的控制信息。根据实施例，SPD设备存储关于存储器模块的配置信息的信息。在实施例中，至少一个集成电路缓冲器设备访问存储在SPD设备中的信息。在封装实施例中，封装容纳集成电路缓冲管芯和多个集成电路存储器管芯。

99. 发明申请

US20070033338A1 Memory with address-differentiated refresh rate to accommodate low-retention storage rows 有权
标题翻译：内存具有地址分辨刷新率，以适应低保留存储行
公开(公告)号：US20070033338A1
公开(公告)日：2007-02-08
申请号：US11198708
申请日：2005-08-04
申请人： Ely Tsern
发明人： Ely Tsern
IPC分类号： G06F13/28
CPC分类号： G11C11/40611 , G11C11/406 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2211/4061
摘要： In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster refresh rate.
摘要翻译：在动态随机存取存储器装置中，经由信令接口接收刷新命令，并且响应于所述刷新命令，以第一刷新率刷新第一行存储单元，并以第二更新刷新刷新第二行存储单元率。

100. 发明申请

US20070030746A1 Memory device testing to support address-differentiated refresh rates 有权
标题翻译：内存设备测试支持地址分辨刷新率
公开(公告)号：US20070030746A1
公开(公告)日：2007-02-08
申请号：US11198689
申请日：2005-08-04
申请人： Scott Best , Ely Tsern
发明人： Scott Best , Ely Tsern
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/401 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2211/4061
摘要： A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.
摘要翻译：一种测试动态随机存取存储器（DRAM）装置的方法，所述动态随机存取存储器（DRAM）装置具有N行存储单元，并且在至少一个操作模式中需要在指定的时间间隔内从外部源接收至少N个刷新命令。在第一次保留测试中测试存储单元行，以识别在指定的时间间隔内不能保留数据的行。在第二次保留测试中测试在指定时间间隔内未能保留数据的行，以识别在缩短的时间间隔内保留数据的行，缩写时间间隔短于指定的时间间隔。

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