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91. 发明授权

US06238957B1 Method of forming a thin film transistor 有权
公开(公告)号：US06238957B1
公开(公告)日：2001-05-29
申请号：US09457206
申请日：1999-12-07
申请人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
IPC分类号： H01L2184
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

92. 发明授权

US06130137A Method of forming a resistor and integrated circuitry having a resistor construction 有权
标题翻译：形成电阻器的方法和具有电阻器结构的集成电路
公开(公告)号：US06130137A
公开(公告)日：2000-10-10
申请号：US170792
申请日：1998-10-13
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/20
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.
摘要翻译：从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

93. 发明授权

US6066528A Method for forming a capacitor compatible with high dielectric constant materials having two independent insulative layers 失效
公开(公告)号：US6066528A
公开(公告)日：2000-05-23
申请号：US314117
申请日：1994-09-27
申请人： Pierre C. Fazan , Gurtej S. Sandhu
发明人： Pierre C. Fazan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/71
CPC分类号： H01L27/11502 , H01L21/76849 , H01L21/7687 , H01L21/76889 , H01L27/10852 , H01L27/11507 , H01L28/60 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.

94. 发明授权

US6049101A Processing methods of forming a capacitor, and capacitor construction 失效
公开(公告)号：US6049101A
公开(公告)日：2000-04-11
申请号：US36702
申请日：1998-03-06
申请人： Thomas M. Graettinger , Paul J. Schuele , Pierre C. Fazan , Li Li , Zhiqiang Wu , Kunal R. Parekh , Thomas Arthur Figura
发明人： Thomas M. Graettinger , Paul J. Schuele , Pierre C. Fazan , Li Li , Zhiqiang Wu , Kunal R. Parekh , Thomas Arthur Figura
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/84
摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

95. 发明授权

US5933754A Semiconductor processing method of forming an electrically conductive contact plug 失效
标题翻译：形成导电接触插头的半导体加工方法
公开(公告)号：US5933754A
公开(公告)日：1999-08-03
申请号：US874642
申请日：1997-06-13
申请人： Viju K. Mathews , Nanseng Jeng , Pierre C. Fazan
发明人： Viju K. Mathews , Nanseng Jeng , Pierre C. Fazan
IPC分类号： H01L21/28 , H01L21/768 , H01L23/14 , H01L23/522 , H01L21/308
CPC分类号： H01L21/76843 , H01L21/76804 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer of conductive material atop the wafer and to within the facet etched contact opening to fill the contact opening; and h) etching the conductive material and first material layer inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate.
摘要翻译：相对于晶片形成导电接触插塞的半导体处理方法包括：a）提供要进行电连接的基板; b）在基板顶部沉积一层第一材料至所选择的厚度; c）图案掩蔽第一材料层以形成所需的接触开口; d）蚀刻通过第一材料层以形成通过其与基板电连接的接触开口，接触开口具有最外区域; e）在蚀刻之后形成接触开口，从第一材料层去除掩模; f）在从第一材料层去除掩模之后，相对于接触开口小面溅射蚀刻到第一材料层中以提供向外成角度的侧壁，这有效地加宽了接触开口最外区域，向外成角度的侧壁具有内部基部，与原来的接触开口; g）在晶片顶部和面蚀刻的接触开口内沉积导电材料层以填充接触开口; 以及h）将所述导电材料和所述第一材料层向内蚀刻到至少所述成角度的侧壁的内部基底，以限定与所述基底电连接的导电接触插塞。

96. 发明授权

US5923078A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5923078A
公开(公告)日：1999-07-13
申请号：US079368
申请日：1998-05-15
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/329 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L29/66166 , H01L27/0629 , H01L27/0802
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

97. 发明授权

US5889300A Capacitor with containers members 失效
标题翻译：电容器与容器成员
公开(公告)号：US5889300A
公开(公告)日：1999-03-30
申请号：US807563
申请日：1997-02-28
申请人： Thomas Figura , Pierre C. Fazan
发明人： Thomas Figura , Pierre C. Fazan
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, with the other of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3. At least one of the first and second layers is selectively etchable relative to the other of the first and second layers to facilitate a container construction and formation of the pedestal disk. Utilization of alternate materials to the doped semiconductive material is also contemplated.
摘要翻译：一种电容器结构包括：a）由中间电容器介电层分隔开的第一和第二导电电容器板，所述第一电容器板包括第一和第二容器构件，所述第二容器构件容纳在所述第一容器构件的内部，所述第一和第二容器构件包括相应的环部分和相应的基部; 以及b）位于所述第一容器构件基部和所述第二容器构件基部的正中方的基座盘，以相对于所述第一容器构件间隔并支撑所述第二容器构件。该结构优选通过使用在其中的容器接触开口内的成型层上设置的一系列交替的半导体材料层来制造。第一层和第二层之一具有大于约5×1019离子/ cm3的平均导电性增强掺杂剂浓度，第一和第二层中的另一层具有从0离子/ cm 3至约5×10 19离子/ cm 3的平均导电性增强掺杂剂浓度。第一层和第二层中的至少一层相对于第一层和第二层中的另一层可选择性地蚀刻，以便于容器构造和基座盘的形成。也考虑了对掺杂半导体材料的替代材料的利用。

98. 发明授权

US5830793A Method of selective texfturing for patterned polysilicon electrodes 失效
标题翻译：图案化多晶硅电极的选择性插拔方法
公开(公告)号：US5830793A
公开(公告)日：1998-11-03
申请号：US579238
申请日：1995-12-28
申请人： Klaus F. Schuegraf , Pierre C. Fazan , Thomas A. Figura
发明人： Klaus F. Schuegraf , Pierre C. Fazan , Thomas A. Figura
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： Polysilicon or amorphous silicon electrodes are selectively texturized with respect to neighboring dielectric surfaces. Selectivity of texturizing is partially accomplished by exploiting differences in seed incubation time on silicon as compared to neighboring surfaces. The texturizing process is made substantially completely selective by a texturizing post-etch, which selectively removes parasitic deposits from surfaces adjacent to the silicon electrodes. Selectively texturized electrodes represent a significant improvement in DRAM process integration.
摘要翻译：多晶硅或非晶硅电极相对于相邻的电介质表面选择性地组织化。通过利用与邻近表面相比硅上种子孵育时间的差异部分地实现了纹理化的选择性。纹理化过程通过纹理化后蚀刻基本上完全选择性，其选择性地去除与硅电极相邻的表面的寄生沉积物。选择性组织化电极代表了DRAM工艺集成的显着改进。

99. 发明授权

US5821150A Method of forming a resistor and integrated circuitry having a resistor construction 失效
公开(公告)号：US5821150A
公开(公告)日：1998-10-13
申请号：US954970
申请日：1997-10-20
申请人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
发明人： Kirk Prall , Pierre C. Fazan , Aftab Ahmad , Howard E. Rhodes , Werner Juengling , Pai-Hung Pan , Tyler Lowrey
IPC分类号： H01L21/02 , H01L27/06 , H01L27/08 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802 , Y10S148/136
摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

100. 发明授权

US5801104A Uniform dielectric film deposition on textured surfaces 失效
标题翻译：纹理表面上均匀的电介质膜沉积
公开(公告)号：US5801104A
公开(公告)日：1998-09-01
申请号：US547561
申请日：1995-10-24
申请人： Klaus F. Schuegraf , Pierre C. Fazan
发明人： Klaus F. Schuegraf , Pierre C. Fazan
IPC分类号： H01L21/02 , H01L21/304 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L28/84 , H01L21/304 , H01L28/40 , H01L27/10852 , Y10S438/928 , Y10S438/941 , Y10S438/964
摘要： Uniformity of thin deposited layers on textured surfaces is enhanced by reducing the total surface area available to film deposition. The backside surface area of a semiconductor wafer is reduced prior to film deposition, thereby reducing the available surface to deposition when a deposition process is supply-limited. Reducing the backside surface area suppresses nonuniformities in thin film deposition when the deposition process is substantially supply-limited. The present invention is advantageous for improving uniformity of nitride capacitor dielectric layers deposited on textured electrodes.
摘要翻译：通过减少可用于薄膜沉积的总表面积，增强纹理表面上的薄沉积层的均匀性。在薄膜沉积之前，半导体晶片的背面表面积减小，从而当沉积过程被供应限制时，减少可用表面沉积。当沉积过程基本上受供料限制时，减小背面表面积抑制薄膜沉积中的不均匀性。本发明对于改善沉积在纹理电极上的氮化物电容器电介质层的均匀性是有利的。

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