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91. 发明申请

US20120079345A1 SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER UNITS IN A TURBO DECODING SYSTEM HAVING PARALLEL DECODING UNITS 有权
标题翻译：用于在具有并行解码单元的涡轮解码系统中分配代码块以构成解码器单元的系统和方法
公开(公告)号：US20120079345A1
公开(公告)日：2012-03-29
申请号：US13313210
申请日：2011-12-07
申请人： Alexander E. Andreev , Sergey Y. Gribok , Vojislav Vukovic
发明人： Alexander E. Andreev , Sergey Y. Gribok , Vojislav Vukovic
IPC分类号： G06F11/10
CPC分类号： H03M13/6561 , H03M13/2957
摘要： A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping.
摘要翻译：一种用于在具有并行解码单元的turbo解码系统中将代码块分配给组成解码单元的系统和方法。在一个实施例中，该方法包括：（1）将turbo解码系统表示为资源图矩形，（2）将码块表示为码块矩形，（3）将码块矩形映射到资源图矩形中，）基于映射将代码块分配给组成解码单元。

92. 发明授权

US07656325B1 Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data 有权
标题翻译：串行器解串器（SerDes）具有主要的数字架构和反序列化数据的方法
公开(公告)号：US07656325B1
公开(公告)日：2010-02-02
申请号：US12169696
申请日：2008-07-09
申请人： Alexander E. Andreev
发明人： Alexander E. Andreev
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L25/03063
摘要： A serializer-deserializer and a method of deserializing data. In one embodiment, the serializer-deserializer includes: (1) an analog-to-digital converter configured to receive a serial data stream and provide a digital output based thereon, (2) a digital comparator coupled to the analog-to-digital converter and configured to compare the digital output to an output table to yield candidate output bits, (3) a digital feedback equalizer coupled to the digital comparator and configured to generate the output table based on the candidate output bits and (4) a multiplexer coupled to the digital comparator and configured to select output bits from among the candidate output bits to form a discrete bit sequence.
摘要翻译：串行器 - 解串器和反序列化数据的方法。在一个实施例中，串行器 - 解串器包括：（1）配置成接收串行数据流并基于其提供数字输出的模拟 - 数字转换器，（2）耦合到模数转换器并且被配置为将数字输出与输出表进行比较以产生候选输出位，（3）数字反馈均衡器，耦合到数字比较器并被配置为基于候选输出位产生输出表，以及（4）耦合到所述数字比较器被配置为从候选输出比特中选择输出比特以形成离散比特序列。

93. 发明授权

US07283385B2 RRAM communication system 失效
标题翻译： RRAM通信系统
公开(公告)号：US07283385B2
公开(公告)日：2007-10-16
申请号：US10999481
申请日：2004-11-30
申请人： Alexander E. Andreev , Sergey Gribok , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Sergey Gribok , Anatoli A. Bolotov
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/4401 , G11C29/56004 , G11C2029/3602 , G11C2029/5602
摘要： The present invention provides a RRAM communication system including at least one RRAM controller and a master controller. The master controller is communicatively coupled to each of at least one RRAM controller. The master controller is suitable for loading test input parameters into at least one RRAM controller, starting execution of a test and obtaining a result of test execution from at least one RRAM controller. Each of at least one RRAM controller is suitable for executing different tests depending on commands received from the master controller.
摘要翻译：本发明提供一种包括至少一个RRAM控制器和主控制器的RRAM通信系统。主控制器通信地耦合到至少一个RRAM控制器中的每一个。主控制器适用于将测试输入参数加载到至少一个RRAM控制器中，开始执行测试并从至少一个RRAM控制器获得测试执行结果。至少一个RRAM控制器中的每一个适合于根据从主控制器接收到的命令执行不同的测试。

94. 发明授权

US07200785B2 Sequential tester for longest prefix search engines 有权
公开(公告)号：US07200785B2
公开(公告)日：2007-04-03
申请号：US10387988
申请日：2003-03-13
申请人： Alexander E. Andreev , Anatoli A. Bolotov
发明人： Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G01R31/28
CPC分类号： G01R31/31917 , Y10S707/99933
摘要： The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for outputting a floating rectangle which may represent a search table of the longest prefix search engine, a coding module for providing address and prefix information to the longest prefix search engine, a mapping module for providing data information to the longest prefix search engine, a super search engine for performing super search operations, and an analyzer for computing predicted outputs of the longest prefix search engine and for comparing the predicted outputs with actual outputs computed by the longest prefix search engine.

95. 发明授权

US07082561B2 Built-in functional tester for search engines 失效
公开(公告)号：US07082561B2
公开(公告)日：2006-07-25
申请号：US10135624
申请日：2002-04-30
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Nikola Radovanovic
IPC分类号： G01R31/28
CPC分类号： G01R31/3183 , G01R31/318378
摘要： A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

96. 发明授权

US06941494B1 Built-in test for multiple memory circuits 有权
标题翻译：内置多个内存测试电路
公开(公告)号：US06941494B1
公开(公告)日：2005-09-06
申请号：US10027311
申请日：2001-12-21
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Lav D. Ivanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Lav D. Ivanovic
IPC分类号： G11C29/00 , G11C29/26
CPC分类号： G11C29/26
摘要： A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.
摘要翻译：存储器测试电路包括用于耦合到存储器件的套环，用于响应于切换信号在外部电路和套环之间切换存储器件的地址总线和数据总线; 以及耦合到所述套环的控制器，用于产生所述切换信号，测试向量以及所述控制器和所述套环之间的控制信号，所述控制器和所述套环在多达七个控制线上，用于使用所述测试向量来测试所述存储器可以同时使用同一控制器测试各种尺寸的多个存储器件。

97. 发明授权

US06785699B1 Prefix comparator 失效
标题翻译：前缀比较器
公开(公告)号：US06785699B1
公开(公告)日：2004-08-31
申请号：US09862000
申请日：2001-05-04
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F700
CPC分类号： G06F17/30985 , Y10S707/99933
摘要： A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.
摘要翻译：基于作为p1和p2的扩展的位串ip1和ip2以及定义p1和p2的长度的二进制字n1和n2来识别两个二进制字p1和p2的最长的公共子扩展。如果p1> p2，则位串和字被处理以设置“较大”的输出，并且如果p1 = p2则设置“相等”的输出。具有具有第一逻辑值的具有连续的具有最高有效位的字符串的掩码被构造以识别p1和p2的匹配子表示。

98. 发明授权

US06665850B1 Spanning tree method for K-dimensional space 失效
标题翻译： K维空间的生成树方法
公开(公告)号：US06665850B1
公开(公告)日：2003-12-16
申请号：US10153570
申请日：2002-05-22
申请人： Alexander E. Andreev , Vojislav Vukovic
发明人： Alexander E. Andreev , Vojislav Vukovic
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in 3-dimensional space. The first and second dimensions are coordinates on a plane, while the third dimension is time which is arrival pin time for buffers insertion and clock latency for clock routing. In a first aspect of the present invention, a method includes partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points. Graph edges are made for the points by connecting each point to its closest points in every of 2K subspaces and the number of graph nodes is then reduced to a predefined value.
摘要翻译：本发明涉及一种用于K维空间的生成树方法。为了解决定时驱动的缓冲插入和时钟路由问题，必须在3维空间中构建点集群。第一和第二维是平面上的坐标，而第三维是时间，即缓冲区插入的到达引脚时间和时钟路由的时钟延迟。在本发明的第一方面，一种方法包括将输入的一组点划分成分区的二叉树，使得每个叶分区具有最大限度的定义数量的点。通过将每个点连接到其在2K个子空间中的每一个中的最接近的点来形成图形边缘，然后将图形节点的数量减少到预定义的值。

99. 发明授权

US06615397B1 Optimal clock timing schedule for an integrated circuit 有权
标题翻译：集成电路的最佳时钟时序表
公开(公告)号：US06615397B1
公开(公告)日：2003-09-02
申请号：US09879380
申请日：2001-06-12
申请人： Alexander E. Andreev , Egor A. Andreev , Ivan Pavisic
发明人： Alexander E. Andreev , Egor A. Andreev , Ivan Pavisic
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/62
摘要： A netlist graph of an IC cell contains cell pin vertices, auxiliary vertices, and edges between vertices having a length. A clock shift SH(V) is assigned to each auxiliary vertex so that for any two auxiliary vertices, a difference between the clock shift of the two auxiliary vertices is no greater than a design time of the two auxiliary vertices. The clock shift is assigned such that SH(V1)+DELAY(V1,V2)−SH(V2)≦f·BOUND(V1,V2), where SH(V1) and SH(V2) are the clock shift of first and second auxiliary vertices, DELAY(V1,V2) is a maximal delay of the path between the first and second auxiliary vertices, f is a minimize constant, and BOUND(V1,V2) is a timing restriction of the first and second auxiliary vertices.
摘要翻译： IC单元格的网表包含单元针顶点，辅助顶点和具有长度的顶点之间的边。时钟偏移SH（V）被分配给每个辅助顶点，使得对于任何两个辅助顶点，两个辅助顶点的时钟偏移之间的差不大于两个辅助顶点的设计时间。分配时钟偏移使得SH（V1）+ DELAY（V1，V2）-SH（V2）<= f.BOUND（V1，V2），其中SH（V1）和SH（V2）是第一个时钟偏移和第二辅助顶点，DELAY（V1，V2）是第一和第二辅助顶点之间的路径的最大延迟，f是最小化常数，BOUND（V1，V2）是第一和第二辅助顶点的定时限制。

100. 发明授权

US06553370B1 Flexible search engine having sorted binary search tree for perfect match 失效
标题翻译：灵活的搜索引擎具有排序二进制搜索树完美匹配
公开(公告)号：US06553370B1
公开(公告)日：2003-04-22
申请号：US09679313
申请日：2000-10-04
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , G06F17/30864 , Y10S707/99933 , Y10S707/99942
摘要： A binary search tree is structured so that keys or addresses associated with data in the bottom vertices are arranged in a predetermined order, such as ascending key address order. The root vertex and each hierarchy vertex contains the lowest value key from each child vertex and are thus similarly arranged by key value order. Each vertex of each level contains at least k and no more than 2k−1 keys, where k is an integer ≦2 and is constant for all vertices of a given level, but may vary between levels. The result is a structured tree having equal path lengths between the root vertex and each bottom vertex for search purposes. Keys are deleted and inserted to the bottom vertices by restructuring the tree under control of computer instructions.
摘要翻译：二叉搜索树被构造成使得与底部顶点中的数据相关联的键或地址以预定顺序排列，例如升序键地址顺序。根顶点和每个层次顶点包含来自每个子顶点的最低值密钥，因此按键值顺序类似地布置。每个级别的每个顶点包含至少k个和不超过2k-1个密钥，其中k是整数<= 2，并且对于给定级别的所有顶点是常数，但是可以在各个级别之间变化。结果是一个结构化的树，其根顶点和每个底部顶点之间的路径长度相等，用于搜索目的。键被删除，并通过在计算机指令的控制下重构树来插入底部顶点。

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