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    • 91. 发明授权
    • Coarse timing synchronization acquisition method in a mobile communication system
    • 移动通信系统中的粗时序同步采集方法
    • US08290002B2
    • 2012-10-16
    • US12679016
    • 2007-12-29
    • Qiang Li
    • Qiang Li
    • H04J3/06
    • H04L27/2656H04L27/2676H04L27/2684
    • A coarse timing synchronization acquisition method in a mobile communication system is applied to the timing synchronization acquisition of a mobile communication system that transmits the same signal blocks repeatedly, which comprises: starting from the beginning time instant of timing synchronization acquisition, iteratively calculating the delay correlation accumulation (DCA) values at K samples, when K is the number of DCA values at each time slot; M time slots are searched in each frame, the position corresponding to the maximum DCA value is taken as the estimate of timing synchronization position; M timing synchronization position estimates are obtained, and among these, one timing synchronization position estimate is selected as the candidate for the current frame timing synchronization position, and it is decided whether the candidate is reliable; after L frames are searched, a predicted timing synchronization position of the next frame is obtained by using the L timing synchronization positions.
    • 移动通信系统中的粗定时同步获取方法被应用于重复发送相同信号块的移动通信系统的定时同步采集,其包括:从定时同步获取的开始时刻开始,迭代地计算延迟相关 当K是每个时隙的DCA值的数量时,K个样本的累积(DCA)值; 在每帧中搜索M个时隙,将对应于最大DCA值的位置作为定时同步位置的估计值; 获得M个定时同步位置估计,其中选择一个定时同步位置估计作为当前帧定时同步位置的候选,并且确定候选是否可靠; 在L帧被搜索之后,通过使用L个定时同步位置来获得下一帧的预测定时同步位置。
    • 93. 发明申请
    • Method and Device for Decoding Reed-Solomon (RS) Code
    • 用于解码里德 - 所罗门(RS)代码的方法和设备
    • US20120166915A1
    • 2012-06-28
    • US13258449
    • 2010-05-04
    • Yueyi YouQiang LiNing QiuNanshan CaoTao Zhang
    • Yueyi YouQiang LiNing QiuNanshan CaoTao Zhang
    • H03M13/07G06F11/10
    • H03M13/1515H03M13/3715H03M13/451H03M13/458H03M13/616
    • The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.
    • 本发明的实施例公开了一种用于对RS码进行解码的方法和装置,该方法包括:接收由信道输出的RS码的比特可靠性信息,对比特可靠性信息进行硬判决以获得硬判决结果 价值序列 根据与RS码的编码模式相对应的初始检查阵列,确定硬判决结果值序列的错误的类型; 根据硬判决结果值序列的错误类型和能够校正错误的纠错模式之间的预设对应关系,确定与硬判决结果值序列的错误类型对应的纠错模式, 以及根据所确定的纠错模式对所述硬判定结果值序列进行位纠错; 在比特纠错之后输出硬判决结果值序列作为解码结果。
    • 95. 发明申请
    • Synchronization Method and Device
    • 同步方法和设备
    • US20120099608A1
    • 2012-04-26
    • US13257920
    • 2010-03-25
    • Yueyi YouQiang LiNing QiuNanshan CaoTao Zhang
    • Yueyi YouQiang LiNing QiuNanshan CaoTao Zhang
    • H04J3/06
    • H04L27/2656H04L27/2675
    • A synchronization method is disclosed, including: obtaining a synchronization symbol position {circumflex over (d)}0 of one time slot of an initial update period; taking Ntrack frames as an update period to adjust the synchronization symbol position, and the step of adjusting the synchronization symbol position including: obtaining a synchronization symbol position {circumflex over ({circumflex over (d)}k+1=dk+Ntrack{circumflex over (T)}k of a corresponding time slot of a (k+1)th update period according to a synchronization symbol position {circumflex over (d)}k of a corresponding time slot of a kth update period and an inter-frame sampling derivation estimation value {circumflex over (T)}k of said kth update period; obtaining synchronization symbol positions of other time slots in said kth update period according to the synchronization symbol position {circumflex over (d)}k of the corresponding time slot of the kth update period and the inter-frame sampling derivation estimation value {circumflex over (T)}k of said kth update period. A synchronization apparatus is also disclosed. The method and apparatus reduces synchronization calculation amount.
    • 公开了一种同步方法,其包括:获得初始更新周期的一个时隙的同步符号位置{(d)} 0; 将Ntrack帧作为更新周期来调整同步符号位置,以及调整同步符号位置的步骤包括:获得同步符号位置{circumflex over({circumflex over(d)} k + 1 = dk + Ntrack {circumflex 根据第k个更新周期的对应时隙的同步符号位置{(d)} k的第(k + 1)个更新周期的相应时隙,超过(T)} k个k 根据所述第k个更新周期的采样导出估计值{(f)(k)),根据相应时隙的同步符号位置{(d)} k获得所述第k个更新周期中的其他时隙的同步符号位置 以及所述第k个更新周期的帧间采样导出估计值(在(T)} k的转换,同时还公开了同步装置,该方法和装置减少了同步计算 nt。
    • 97. 发明授权
    • Method and system for calibrating a plurality of modules in a communication system
    • 用于在通信系统中校准多个模块的方法和系统
    • US08102953B2
    • 2012-01-24
    • US11618721
    • 2006-12-29
    • Razieh RoufoogaranArya BehzadQiang Li
    • Razieh RoufoogaranArya BehzadQiang Li
    • H04L27/08H04B1/18
    • H04B1/0082H03G1/0035H03G3/30
    • A method and system for calibrating a plurality of modules in a communication system is provided. The method may include selecting a plurality of modules with at least one output signal and calibrating an amplitude of each selected module to be within a specified range if the amplitude is out of the specified range via a gain control processing circuit of the selected module, wherein the plurality of modules may be calibrated in an order starting with a first module located at an input of a signal path and ending with a module located at an output of the signal path. The DC component and amplitude of the envelope of the output signal may be detected by circuitry within the selected module. Muxes may be utilized to route the DC component and amplitude of the envelope to a feedback control processing circuit.
    • 提供了一种用于在通信系统中校准多个模块的方法和系统。 该方法可以包括:通过所选择的模块的增益控制处理电路,如果振幅超出指定范围,则选择具有至少一个输出信号的多个模块,并将每个所选模块的振幅校准在指定范围内,其中 多个模块可以以从位于信号路径的输入端的第一模块开始并以位于信号路径的输出端的模块结束的顺序被校准。 输出信号的包络的直流分量和振幅可由所选模块内的电路检测。 可以利用复用器将DC分量和信号的幅度路由到反馈控制处理电路。
    • 98. 发明申请
    • ON-CHIP CAPACITOR STRUCTURE
    • 片上电容结构
    • US20120007215A1
    • 2012-01-12
    • US13236536
    • 2011-09-19
    • Hooman DarabiQiang LiBo Zhang
    • Hooman DarabiQiang LiBo Zhang
    • H01L27/06
    • H01L28/40H01L23/5223H01L27/0805H01L28/87H01L28/91H01L29/93H01L29/94H01L2924/0002H01L2924/00
    • At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.
    • 至少第一电容器形成在衬底上并连接到差分电路的第一差分节点,并且第一电容器可以是可变电容的。 第二电容器形成在衬底上并连接到差分电路的第二差分节点,并且第二电容器也可以是可变的。 第三电容器连接在第一差分节点和第二差分节点之间,并且至少部分地形成在第一电容器的上方。 以这种方式,可以在衬底上减小第一电容器和/或第二电容器的尺寸,并且可以响应于一个或多个电路的可变特性来调整第一和/或第二电容器的电容 差分电路的组件。
    • 99. 发明申请
    • Configurable Clock Signal Generator
    • 可配置时钟信号发生器
    • US20110018604A1
    • 2011-01-27
    • US12539495
    • 2009-08-11
    • Yuyu ChangQiang LiJohn LeeteHooman DarabiYiannis Kokolakis
    • Yuyu ChangQiang LiJohn LeeteHooman DarabiYiannis Kokolakis
    • H03L5/00
    • H03L1/00H03B5/368
    • A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.
    • 本文描述了提供低功率时钟信号或低噪声时钟信号的方法。 确定是否使用低功率模式或低噪声模式。 低压差稳压器(LDO)的参考电压输入端被切换到低功耗模式的低功耗参考电压,低噪声模式的低噪声电压基准用。 LDO为晶体振荡器提供恒定电压输出。 使用晶体振荡器产生时钟信号。 使用低功率限幅器来限制时钟信号以产生低功率输出时钟信号和/或使用低噪声限制器来限制以产生低噪声时钟信号。 使用多路复用器选择低功耗输出时钟信号或低噪声输出时钟信号。