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91. 发明授权

US07461199B2 Pipelined parallel programming operation in a non-volatile memory system 有权
标题翻译：在非易失性存储器系统中进行流水线并行编程操作
公开(公告)号：US07461199B2
公开(公告)日：2008-12-02
申请号：US11611706
申请日：2006-12-15
申请人： Kevin M. Conley , Yoram Cedar
发明人： Kevin M. Conley , Yoram Cedar
IPC分类号： G06F5/06 , G11C7/10 , G11C16/06
CPC分类号： G11C16/105 , G11C16/10 , G11C16/102 , G11C2216/22
摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.
摘要翻译：本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。数据从控制器传送到第一存储器芯片，并且开始编程操作。当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。呈现了两组实施例，一种将缓冲器中的主机数据保留，直到该数据的成功编程被确认为止，并且不需要实现该成功，并且不保留数据从而实现更高的数据编程吞吐量。

92. 发明申请

US20080123419A1 Methods of Varying Read Threshold Voltage in Nonvolatile Memory 有权
标题翻译：在非易失性存储器中改变读取阈值电压的方法
公开(公告)号：US20080123419A1
公开(公告)日：2008-05-29
申请号：US11556615
申请日：2006-11-03
申请人： Yigal Brandman , Kevin M. Conley
发明人： Yigal Brandman , Kevin M. Conley
IPC分类号： G11C16/00 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1072 , G11C16/26 , G11C16/349
摘要： Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.
摘要翻译：使用在存储器寿命期间调整的一个或多个读取电压从非易失性存储器阵列读取数据。编程目标电压和读取电压可以在存储器寿命中一起调整，以将存储器状态映射到越来越宽的阈值窗口。单个内存状态映射到更广泛的子范围，从而减少错误。

93. 发明授权

US07379330B2 Retargetable memory cell redundancy methods 有权
标题翻译：可重定位的存储单元冗余方法
公开(公告)号：US07379330B2
公开(公告)日：2008-05-27
申请号：US11270198
申请日：2005-11-08
申请人： Kevin M. Conley , Yoram Cedar
发明人： Kevin M. Conley , Yoram Cedar
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C29/81 , G11C16/0483 , G11C16/16 , G11C29/808 , G11C29/82
摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.
摘要翻译：在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。重新映射作为初始测试和配置的一部分完成。具体硬件可用于方案或固件在内存控制器中可实现的方案。

94. 发明授权

US07362613B2 Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks 有权
标题翻译：闪存EEPROM系统具有同时多个数据扇区编程和存储其他指定块中的物理块特性
公开(公告)号：US07362613B2
公开(公告)日：2008-04-22
申请号：US11679012
申请日：2007-02-26
申请人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
发明人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
IPC分类号： G11C16/04
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7203 , G06F2212/7207 , G06F2212/7208 , G11C16/10 , G11C16/3459 , G11C29/82 , G11C2216/14
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.
摘要翻译：非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。该系统包括可以单独地或以各种协作组合实现的多个特征。一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围，使得容易制造具有不同容量的存储器芯片的存储器系统。存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

95. 发明授权

US07171513B2 Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory 有权
标题翻译：用于操作具有与存储器的页面和/或块的大小不同的大小的数据扇区的非易失性存储器系统的技术
公开(公告)号：US07171513B2
公开(公告)日：2007-01-30
申请号：US10727759
申请日：2003-12-03
申请人： Carlos Gonzalez , Kevin M. Conley , Eliyahou Harari
发明人： Carlos Gonzalez , Kevin M. Conley , Eliyahou Harari
IPC分类号： G06F12/02
CPC分类号： G06F12/04 , G06F12/0246 , G06F2212/7209
摘要： A non-volatile memory system, such as a flash EEPROM system, is disclosed to be divided into a plurality of blocks and each of the blocks into one or more pages, with sectors of data being stored therein that are of a different size than either the pages or blocks. One specific technique packs more sectors into a block than pages provided for that block. Error correction codes and other attribute data for a number of user data sectors are preferably stored together in different pages and blocks than the user data.
摘要翻译：公开了一种诸如闪存EEPROM系统的非易失性存储器系统，其被划分为多个块和每个块到一个或多个页面，其中存储数据扇区的大小不同于任何一个页面或块。一个特定的技术将更多的扇区包含在块中，而不是为该块提供的页面。用于多个用户数据扇区的纠错码和其他属性数据优选地存储在与用户数据不同的页面和块中。

96. 发明授权

US07149871B2 Zone boundary adjustment for defects in non-volatile memories 有权
标题翻译：非易失性存储器缺陷区域边界调整
公开(公告)号：US07149871B2
公开(公告)日：2006-12-12
申请号：US11114996
申请日：2005-04-26
申请人： Kevin M. Conley
发明人： Kevin M. Conley
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/4401 , G11C29/76 , G11C29/808
摘要： A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.
摘要翻译：非易失性存储器由卡控制器分为逻辑区，以减小其用于地址转换的数据结构的大小。调整区域边界以适应内存测试允许的缺陷，以提高卡片产量并调整现场边界以延长卡片的使用寿命。固件扫描卡上有缺陷块的存在。一旦知道这些块的位置，固件就会以这样一种方式计算区域边界，使得块在这些区域之间平均分配。由于良好块的数量符合内存测试标准的卡片测试标准，因此缺陷会降低卡片的成品率。控制器可以进行动态边界调整。当发生缺陷时，控制器可以再次执行分析，如果需要，可重新分配区域边界，移动任何用户数据。

97. 发明授权

US06873549B2 Writable tracking cells 有权
公开(公告)号：US06873549B2
公开(公告)日：2005-03-29
申请号：US10692922
申请日：2003-10-23
申请人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
发明人： Shahzad B. Khalid , Daniel C. Guterman , Geoffrey S. Gongwer , Richard Simko , Kevin M. Conley
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C27/00 , G11C29/04
CPC分类号： G11C16/28 , G11C7/06 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C27/005 , G11C2211/5621 , G11C2211/5634
摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

98. 发明授权

US06763424B2 Partial block data programming and reading operations in a non-volatile memory 有权
公开(公告)号：US06763424B2
公开(公告)日：2004-07-13
申请号：US09766436
申请日：2001-01-19
申请人： Kevin M. Conley
发明人： Kevin M. Conley
IPC分类号： G06F1200
CPC分类号： G11C16/102 , G06F12/0246 , G06F2212/1016 , G06F2212/1032 , G06F2212/7202 , G06F2212/7208 , G06F2212/7209 , G11C16/105 , G11C2216/16
摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

99. 发明授权

US06434044B1 Method and system for generation and distribution of supply voltages in memory systems 有权
标题翻译：用于存储器系统中电源电压的生成和分配的方法和系统
公开(公告)号：US06434044B1
公开(公告)日：2002-08-13
申请号：US09788120
申请日：2001-02-16
申请人： Geoffrey Steven Gongwer , Kevin M. Conley , Chi-Ming Wang , Yong Liang Wang , Raul Adrian Cernea
发明人： Geoffrey Steven Gongwer , Kevin M. Conley , Chi-Ming Wang , Yong Liang Wang , Raul Adrian Cernea
IPC分类号： G11C1604
CPC分类号： G11C5/14
摘要： Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.
摘要翻译：描述了在具有多个存储器块（例如，存储器芯片）的存储器系统内产生和提供各种电压电平的技术。各种电压电平可以由存储器系统内的电压产生电路（例如电荷泵和/或调节器电路）产生。各种电压电平可以通过电源总线提供给多个存储器块。根据一个方面，电荷泵和/或调节器电路设置在存储器系统的至多一个存储器块内（除非提供用于容错的备用），并且使用电源总线来分配所产生的电压电平到其他内存块。根据另一方面，存储器控制器产生多个电源电压电平，其被分配（例如，经由电源总线）到每个存储器块。

100. 发明授权

US06426893B1 Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks 有权
标题翻译：闪存eeprom系统具有同时多个数据扇区编程和存储其他指定块中的物理块特性
公开(公告)号：US06426893B1
公开(公告)日：2002-07-30
申请号：US09505555
申请日：2000-02-17
申请人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
发明人： Kevin M. Conley , John S. Mangan , Jeffrey G. Craig
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7203 , G06F2212/7207 , G06F2212/7208 , G11C16/10 , G11C16/3459 , G11C29/82 , G11C2216/14
摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.
摘要翻译：非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。该系统包括可以单独地或以各种协作组合实现的多个特征。一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围，使得容易制造具有不同容量的存储器芯片的存储器系统。存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

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