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91. 发明授权

US07576393B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07576393B2
公开(公告)日：2009-08-18
申请号：US11476595
申请日：2006-06-29
申请人： Syotaro Ono , Wataru Saito
发明人： Syotaro Ono , Wataru Saito
IPC分类号： H01L23/62
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7806 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a pillar layer including first semiconductor pillars of a first conduction type and second semiconductor pillars of a second conduction type formed laterally, periodically and alternately. The first and second semiconductor pillars include a plurality of diffusion layers formed in a third semiconductor layer as coupled along the depth. The diffusion layers have lateral widths varied at certain periods along the depth. An average of the lateral widths of the diffusion layers in one certain period is made almost equal to another between different periods.
摘要翻译：半导体器件包括：柱层，其包括第一导电类型的第一半导体柱和第二导电类型的第二半导体柱，所述第二导电类型横向，周期性地和交替地形成。第一和第二半导体柱包括沿着深度耦合形成在第三半导体层中的多个扩散层。扩散层的横向宽度在沿深度的某些周期变化。在一定时间段内扩散层的横向宽度的平均值在不同周期之间几乎等于另一个。

92. 发明申请

US20090090968A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20090090968A1
公开(公告)日：2009-04-09
申请号：US12243280
申请日：2008-10-01
申请人： Syotaro ONO , Wataru Saito
发明人： Syotaro ONO , Wataru Saito
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/404
摘要： A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region.
摘要翻译：半导体装置包括：第一导电类型的半导体层; 设置在所述半导体层的前侧的第一主电极; 设置在所述半导体层的背面的第二主电极，所述背面与所述前侧相反; 在第一主电极和第二主电极之间沿垂直方向形成有主电流路径的器件区域外的边缘终端区域的半导体层的表面部分中设置的多个第二导电类型的半导体区域 ; 以及设置在边缘终端区域中的半导体层中的与半导体区域间隔开并且彼此间隔开的第二导电类型的多个掩埋半导体区域。基本上与半导体层的前侧相同的深度设置的掩埋半导体区域被编号为第一，第二。。。第n个从靠近器件区的一个顺序地，与半导体层的前侧不同的深度设置的第n个埋入半导体区域相对于相应的第n个半导体区域朝向器件区域移位，位于半导体层的前侧较深的掩埋半导体区域朝向器件区域更大地移位。

93. 发明授权

US07462909B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07462909B2
公开(公告)日：2008-12-09
申请号：US11453997
申请日：2006-06-16
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to form a first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.
摘要翻译：第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层被布置在第一导电类型的第一半导体层上，在第一周期上周期性地和周期性地交替地形成第一柱层。第二导电类型的第一导电类型的第三半导体柱层和第二导电类型的第四半导体柱层在第一柱层上以比第一周期小的周期性地交替布置在第一柱层上，以形成第二柱层。在第四半导体柱层的表面上形成第二导电类型的半导体基底层。在半导体基底层的表面上形成第一导电类型的半导体扩散层。

94. 发明申请

US20080290403A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080290403A1
公开(公告)日：2008-11-27
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

95. 发明申请

US20080246085A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080246085A1
公开(公告)日：2008-10-09
申请号：US12050405
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono
发明人： Wataru Saito , Syotaro Ono
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/7811
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer that are provided above the first semiconductor layer and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layers and connected to the third semiconductor layer; a fifth semiconductor layer; a control electrode; a gate insulating film; a first main electrode; and a second main electrode. An array period of the fourth semiconductor layers is larger than an array period of the second semiconductor layers. A thickness of a part of the gate insulating film disposed in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of a part of the gate insulating film disposed in the immediate upper region of the fourth semiconductor layer. Sheet impurity concentrations of the second semiconductor layer and the third semiconductor layer that are located in the central portion are higher than a sheet impurity concentration of the third semiconductor layer disposed in an immediately lower region of the fourth semiconductor layer.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，其设置在所述第一半导体层的上方，并且沿着与所述第一半导体层的上表面平行的方向配置; 多个第四半导体层，设置在所述第三半导体层的一些上部区域上，并连接到所述第三半导体层; 第五半导体层; 控制电极; 栅极绝缘膜; 第一主电极; 和第二主电极。第四半导体层的阵列周期大于第二半导体层的阵列周期。设置在第四半导体层之间的中心部分的直接上部区域中的栅极绝缘膜的一部分的厚度比设置在第四半导体层的直接上部区域中的栅极绝缘膜的一部分的厚度厚。位于中心部分的第二半导体层和第三半导体层的片状杂质浓度高于设置在第四半导体层的紧邻下部区域中的第三半导体层的片状杂质浓度。

96. 发明授权

US07271477B2 Power semiconductor device package 失效
标题翻译：功率半导体器件封装
公开(公告)号：US07271477B2
公开(公告)日：2007-09-18
申请号：US10867758
申请日：2004-06-16
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L23/02
CPC分类号： H01L24/41 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L25/074 , H01L2224/32245 , H01L2224/37124 , H01L2224/37147 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73221 , H01L2224/73253 , H01L2224/73257 , H01L2224/83801 , H01L2224/84801 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45147 , H01L2924/00012
摘要： A power semiconductor device package according to one aspect of the present invention comprises: a plurality of power semiconductor chips which are arranged in a laminated structure so that the plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another, and are sealed in a sealing resin as one body.
摘要翻译：根据本发明的一个方面的功率半导体器件封装包括：多个功率半导体芯片，它们以层叠结构布置，使得多个功率半导体芯片在具有相同电结构的表面处彼此相对，并且彼此并联连接，并且作为一体被密封在密封树脂中。

97. 发明申请

US20060231917A1 Semiconductor device 失效
公开(公告)号：US20060231917A1
公开(公告)日：2006-10-19
申请号：US11399448
申请日：2006-04-07
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11

98. 发明申请

US20060157813A1 Power semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060157813A1
公开(公告)日：2006-07-20
申请号：US11250441
申请日：2005-10-17
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/407 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A power semiconductor device has a first main electrode formed along a surface of a substrate, a first semiconductor layer of first conductive type electrically connected to the first main electrode, a cyclic structure section which is formed on the first semiconductor layer and has second semiconductor layers of first conductive type and third semiconductor layers of second conductive type alternately and cyclically formed along the surface of the substrate, a fourth semiconductor layer of second conductive type selectively formed on a part of the second and third semiconductor layers, a fifth semiconductor layer of first conductive type selectively formed on the fourth semiconductor layer, a second main electrode contacted the fourth and fifth semiconductor layers, a control electrode disposed adjacent via a first insulating film on the second, fourth and fifth semiconductor layers, and a depletion layer blocking section which is formed outside of the cyclic structure section and prevents a depletion layer from spreading outside, wherein the depletion layer blocking section includes a conductive layer formed via a second insulating film in a first trench formed outside of the outermost third semiconductor layer in the cyclic structure section.

99. 发明申请

US20060017096A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060017096A1
公开(公告)日：2006-01-26
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L31/113
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

100. 发明申请

US20060011915A1 Nitride semiconductor device 失效
标题翻译：氮化物半导体器件
公开(公告)号：US20060011915A1
公开(公告)日：2006-01-19
申请号：US11014869
申请日：2004-12-20
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/04
CPC分类号： H01L29/402 , H01L29/1066 , H01L29/2003 , H01L29/404 , H01L29/41725 , H01L29/432 , H01L29/517 , H01L29/7786
摘要： A nitride semiconductor device according to one embodiment of the present invention comprises: a non-doped first aluminum gallium nitride (AlxGa1-xN (0≦x≦1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0≦x≦1,x
摘要翻译：根据本发明的一个实施方案的氮化物半导体器件包括：非掺杂的第一氮化镓铝（Al x Ga 1-x N）（0 <= x < = 1））层，其形成为沟道层; 非掺杂或n型第二氮化镓铝（Al x Ga 1-y N）（0≤x≤1，x

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