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91. 发明授权

US08269537B2 Data transfer circuit and method with compensated clock jitter 有权
标题翻译：具有补偿时钟抖动的数据传输电路和方法
公开(公告)号：US08269537B2
公开(公告)日：2012-09-18
申请号：US12754794
申请日：2010-04-06
申请人： Seung Jun Bae , Kwang II Park , Young-Sik Kim , Sang Hyup Kwak
发明人： Seung Jun Bae , Kwang II Park , Young-Sik Kim , Sang Hyup Kwak
IPC分类号： H03L7/00
CPC分类号： H03K5/1565 , H03K2005/0013
摘要： A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.
摘要翻译：用于集成电路装置的数据I / O接口包括接收电源电压的噪声检测器，检测电源电压噪声分量，以及响应于检测到的电源电压噪声分量提供时钟延迟控制信号。数据I / O接口还包括响应于时钟延迟控制信号提供延迟时钟信号的时钟延迟电路和由电源电压供电并且与延迟的时钟信号同步地提供输出数据的数据传输电路。

92. 发明授权

US08254201B2 Semiconductor memory device having power-saving effect 有权
标题翻译：具有省电效果的半导体存储器件
公开(公告)号：US08254201B2
公开(公告)日：2012-08-28
申请号：US12797791
申请日：2010-06-10
申请人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
发明人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1084 , G11C8/18 , G11C2207/2227 , G11C2207/2272
摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。存储单元阵列包括多个存储单元，并被配置为存储数据。当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号设备。数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

93. 发明授权

US08199035B2 Method, device, and system for data communication with preamble for reduced switching noise 有权
标题翻译：用于与前同步码进行数据通信以减少开关噪声的方法，设备和系统
公开(公告)号：US08199035B2
公开(公告)日：2012-06-12
申请号：US13069259
申请日：2011-03-22
申请人： Seung-Jun Bae , Kwang-Chol Choe , Se-Won Seo
发明人： Seung-Jun Bae , Kwang-Chol Choe , Se-Won Seo
IPC分类号： H03M7/00
CPC分类号： H03M5/145
摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.
摘要翻译：数据通信设备或系统包括前同步码单元和数据接口。前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。

94. 发明授权

US08159275B2 Phase-locked loop and bias generator 有权
标题翻译：锁相环和偏置发生器
公开(公告)号：US08159275B2
公开(公告)日：2012-04-17
申请号：US12627730
申请日：2009-11-30
申请人： Young-Sik Kim , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Young-Sik Kim , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： H03L7/06
CPC分类号： H03L7/08
摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.
摘要翻译：提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。在PLL中，使用稳压器驱动压控振荡器。将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

95. 发明申请

US20120087194A1 DATA WRITE TRAINING METHOD AND SEMICONDUCTOR DEVICE PERFORMING THE SAME 有权
标题翻译：数据写入训练方法和执行相同的半导体器件
公开(公告)号：US20120087194A1
公开(公告)日：2012-04-12
申请号：US13270710
申请日：2011-10-11
申请人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
发明人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1087 , G11C7/1093 , G11C2207/2254
摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.
摘要翻译：实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据数据线。在不附加训练命令的情况下执行发送第一写入数据。

96. 发明申请

US20120086490A1 INTEGRATED CIRCUIT DEVICES USING POWER SUPPLY CIRCUITS WITH FEEDBACK FROM A REPLICA LOAD 有权
标题翻译：使用电源电路的集成电路装置与反馈装置的反馈
公开(公告)号：US20120086490A1
公开(公告)日：2012-04-12
申请号：US13240635
申请日：2011-09-22
申请人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
发明人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
IPC分类号： H03K3/023 , G05F1/10
CPC分类号： H03K19/00361 , G05F1/575
摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.
摘要翻译：集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

97. 发明授权

US08151010B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
标题翻译：实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法
公开(公告)号：US08151010B2
公开(公告)日：2012-04-03
申请号：US12902328
申请日：2010-10-12
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

98. 发明授权

US08115739B2 Touch screen device and operating method thereof 有权
公开(公告)号：US08115739B2
公开(公告)日：2012-02-14
申请号：US11785399
申请日：2007-04-17
申请人： Ho Joo Park , Seung Jun Bae , Yoon Hee Koo , Seong Cheol Kang
发明人： Ho Joo Park , Seung Jun Bae , Yoon Hee Koo , Seong Cheol Kang
IPC分类号： G06F3/041
CPC分类号： G06F3/0416 , G06F3/04883 , H04M1/66 , H04M2250/22 , H04R1/10 , H04R1/1041
摘要： A touch screen device and an operating method thereof are provided. More specifically, a touch screen device is provided which allows a user to selectively restrict input through a touch screen. The touch screen device includes a screen that includes a display configured to display images thereon and a detector configured to detect a touch on the display and convert the touch into an electrical signal, and a controller configured to cause images to be displayed on the display and receive and process signals from the detector. Further, a user may determine whether the controller is operated according to the signal input into the detector. The determination may be made either by a switch separately installed on an earphone or by inputting a signal into the detector by a user.

99. 发明授权

US08028251B2 Touch screen device and method of selecting files thereon 有权
标题翻译：触摸屏设备及其上选择文件的方法
公开(公告)号：US08028251B2
公开(公告)日：2011-09-27
申请号：US11646598
申请日：2006-12-28
申请人： Ho Joo Park , Ji Suk Chae , Young Ho Ham , Kyung Hee Yoo , Ji Ae Kim , Yu Mi Kim , Sang Hyun Shin , Seung Jun Bae , Yoon Hee Koo , Jun Hee Kim , Seong Cheol Kang
发明人： Ho Joo Park , Ji Suk Chae , Young Ho Ham , Kyung Hee Yoo , Ji Ae Kim , Yu Mi Kim , Sang Hyun Shin , Seung Jun Bae , Yoon Hee Koo , Jun Hee Kim , Seong Cheol Kang
IPC分类号： G06F3/033
CPC分类号： G06F3/04883 , G06F3/0485
摘要： A touch screen device and a method of operation are provided. The device and method allow for scrolling and selection of files from a file list, and for skipping or reversing an execution order of the selected files simply by performing a drag on a touch screen. The method of selecting files on the touch screen device includes detecting a diagonal drag on a screen, selecting file(s) included within a corresponding range, and skipping file(s) within the range. The method may also include changing an execution order of the selected file(s) when a drag with a return trajectory is detected. The method may also include scrolling through the file list in accordance with a direction and speed of the drag. The device and method allows a plurality of files to be selected and skipped at a time, and a desired file to be rapidly and easily located.
摘要翻译：提供了一种触摸屏设备和操作方法。设备和方法允许从文件列表滚动和选择文件，并且仅通过在触摸屏上执行拖动来跳过或反转所选文件的执行顺序。在触摸屏设备上选择文件的方法包括检测屏幕上的对角线拖动，选择包括在相应范围内的文件以及跳过该范围内的文件。该方法还可以包括当检测到具有返回轨迹的拖动时，改变所选择的文件的执行顺序。该方法还可以包括根据拖动的方向和速度滚动文件列表。该设备和方法允许一次选择和跳过多个文件，并且所需的文件被快速且容易地定位。

100. 发明授权

US08004328B2 AC-coupling phase interpolator and delay-locked loop using the same 失效
标题翻译：交流耦合相位内插器和使用其的延迟锁定环路
公开(公告)号：US08004328B2
公开(公告)日：2011-08-23
申请号：US12570186
申请日：2009-09-30
申请人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
发明人： Jin-Gook Kim , Kwang-II Park , Seung-Jun Bae , Si-Hong Kim , Dae-Hyun Chung
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03K5/13 , H03K2005/00052 , H03L7/0814
摘要： An AC-coupling phase interpolator and a DLL using the same are provided. The AC-coupling phase interpolator includes a coupling capacitor generating and outputting a coupling signal by AC-coupling to an interpolation signal obtained by phase-interpolating an input signal. Thereby, it is possible to correct duty of an input signal and adjust the level of an output signal.
摘要翻译：提供AC耦合相位内插器和使用它的DLL。 AC耦合相位内插器包括耦合电容器，其通过AC耦合产生并输出耦合信号，所述耦合信号通过对输入信号进行相位插值而获得。由此，可以校正输入信号的占空比并调整输出信号的电平。

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