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91. 发明申请

US20100169609A1 Method for optimizing voltage-frequency setup in multi-core processor systems 有权
标题翻译：用于优化多核处理器系统中的电压 - 频率设置的方法
公开(公告)号：US20100169609A1
公开(公告)日：2010-07-01
申请号：US12317845
申请日：2008-12-30
申请人： Lev Finkelstein , Yossi Abulafia , Aviad Cohen , Ronny Ronen , Doron Rajwan , Efraim Rotem
发明人： Lev Finkelstein , Yossi Abulafia , Aviad Cohen , Ronny Ronen , Doron Rajwan , Efraim Rotem
IPC分类号： G06F15/76 , G06F1/00 , G06F9/02
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.
摘要翻译：提供了一种用于动态操作多核处理器系统的方法。该方法包括确定当前活动的处理器核心，识别具有最低工作频率的当前活动的处理器核心，以及根据与所识别的处理器核心相对应的电压 - 频率特性来调整至少一个操作参数，以实现预定义的功能模式，例如。电源优化模式，性能优化模式和混合模式。

92. 发明授权

US07689804B2 Selectively protecting a register file 失效
标题翻译：选择性地保护寄存器文件
公开(公告)号：US07689804B2
公开(公告)日：2010-03-30
申请号：US11642337
申请日：2006-12-20
申请人： Xavier Vera , Jaume Abella , Jose-Alejandro Pineiro , Antonio Gonzalez , Ronny Ronen
发明人： Xavier Vera , Jaume Abella , Jose-Alejandro Pineiro , Antonio Gonzalez , Ronny Ronen
IPC分类号： G06F12/10
CPC分类号： G06F11/1008
摘要： In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种方法，用于如果该值预测将在第一时间段内使用，则保护要存储在具有第一保护等级的寄存器文件的寄存器中的值，并且用如果该值被预测用于第二时间段，则为第二级保护。描述和要求保护其他实施例。

93. 发明授权

US07653786B2 Power reduction for processor front-end by caching decoded instructions 失效
标题翻译：处理器前端通过缓存解码指令进行功耗降低
公开(公告)号：US07653786B2
公开(公告)日：2010-01-26
申请号：US11589803
申请日：2006-10-31
申请人： Baruch Solomon , Ronny Ronen , Doron Orenstien
发明人： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC分类号： G06F12/08
CPC分类号： G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
摘要： A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
摘要翻译：用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。如果指令查找表示未命中，则其后的禁用电路可以被使能。

94. 发明授权

US07586281B2 Methods and apparatus for optimal voltage and frequency control of thermally limited systems 失效
标题翻译：用于最佳电压和频率控制的受热系统的方法和装置
公开(公告)号：US07586281B2
公开(公告)日：2009-09-08
申请号：US11459407
申请日：2006-07-24
申请人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
发明人： Aviad Cohen , Lev Finkelstein , Avi Mendelson , Ronny Ronen , Dmitry Rudoy
IPC分类号： G05D23/00
CPC分类号： H02H6/005 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y10S388/934
摘要： Methods, apparatus, and articles of manufacture control a device or system that has an operational limit related to the rate or frequency of operation. The frequency of operation is controlled at a variable rate calculated to maximize the system or apparatus performance over a calculated period of time short enough that a controlling factor, such as power consumption, does not vary significantly during the period. Known system parameters, such as thermal resistance and capacitance of an integrated circuit (IC) and its package, and measured values, such as current junction temperature in an IC, are used to calculate a time-dependent frequency of operation for the upcoming time period that results in the best overall performance without exceeding the operational limit, such as the junction temperature.
摘要翻译：方法，装置和制品控制具有与操作速率或频率相关的操作限制的装置或系统。操作频率被控制为可变速率，其被计算为在足够长的计算时间段内最大化系统或设备性能，使得诸如功率消耗的控制因素在该时段期间不显着变化。使用已知的系统参数，例如集成电路（IC）及其封装的热阻和电容以及IC中的当前结温等测量值来计算即将到来的时间段的时间依赖性操作频率这导致最佳的整体性能，而不超过操作限制，如结温。

95. 发明授权

US07539850B2 Enhanced virtual renaming scheme and deadlock prevention therefor 失效
标题翻译：增强的虚拟重命名方案和防止死锁
公开(公告)号：US07539850B2
公开(公告)日：2009-05-26
申请号：US10351444
申请日：2003-01-27
申请人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
发明人： Stephan J. Jourdan , Ronny Ronen , Michael Bekerman
IPC分类号： G06F9/34
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
摘要翻译：在处理器内的增强型虚拟重命名方案中，可以将多个逻辑寄存器映射到单个物理寄存器。值缓存确定根据程序指令生成的新值是否与先前执行的指令相关联的值匹配。如果是，则与新执行的指令相关联的逻辑寄存器共享物理寄存器。此外，死锁预防措施可以以在处理器核心中产生来自旧指令的值产生时从较小执行指令“窃取”物理寄存器的方式集成到寄存器分配单元中。

96. 发明申请

US20070061021A1 Combining power prediction and optimal control approaches for performance optimization in thermally limited designs 有权
标题翻译：结合功率预测和优化控制方法进行热限制设计中的性能优化
公开(公告)号：US20070061021A1
公开(公告)日：2007-03-15
申请号：US11224568
申请日：2005-09-12
申请人： Aviad Cohen , Adam De La Zerda , Lev Finkelstein , Ronny Ronen , Dmitry Rudoy
发明人： Aviad Cohen , Adam De La Zerda , Lev Finkelstein , Ronny Ronen , Dmitry Rudoy
IPC分类号： G05B13/02 , G01M1/38
CPC分类号： G05B13/026
摘要： The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.
摘要翻译：电子系统的运行速率最大化，而不超过热约束，例如集成电路（IC）或电子系统的其他部分的最大结温。基于先前测量的与操作参数水平的热性能关系，计算控制系统的热输出的系统的操作参数，用于即将到来的时间段。如果预测的热性能将超过热约束的最大允许水平，则将运行参数减少计算的量，以将热约束保持在刚好低于最大允许水平的水平，从而导致最佳化控制方法系统性能不超过热约束。

97. 发明申请

US20070050554A1 Power reduction for processor front-end by caching decoded instructions 失效
标题翻译：处理器前端通过缓存解码指令进行功耗降低
公开(公告)号：US20070050554A1
公开(公告)日：2007-03-01
申请号：US11589803
申请日：2006-10-31
申请人： Baruch Solomon , Ronny Ronen , Doron Orenstien
发明人： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
摘要： A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
摘要翻译：用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。如果指令查找表示未命中，则其后的禁用电路可以被使能。

98. 发明授权

US07171543B1 Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor 有权
标题翻译：通过将应用程序限制在64位处理器中的32位地址空间子集来执行32位应用程序的方法和装置
公开(公告)号：US07171543B1
公开(公告)日：2007-01-30
申请号：US09536452
申请日：2000-03-28
申请人： Ronny Ronen , Alexander Peleg
发明人： Ronny Ronen , Alexander Peleg
IPC分类号： G06F9/34
CPC分类号： G06F9/3017 , G06F9/342
摘要： Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.
摘要翻译：执行端口到第二位大小环境的第一位大小的应用的指令的装置和方法，包括将应用限制到第一位大小地址空间子集的方法和装置。根据本发明的实施例包括将应用限制到地址空间子集的方法，所述方法包括确定所述应用被限制在第一位大小地址子集中，所述应用包括指令; 生成第二位大小的地址参考作为指令的执行的一部分; 将所生成的地址引用从第二位大小截断到第一位大小; 以及至少部分地基于地址格式控制标志将截断的所生成的地址引用从第一位大小扩展到第二位大小。

99. 发明授权

US07155599B2 Method and apparatus for a register renaming structure 有权
标题翻译：一种寄存器重命名结构的方法和装置
公开(公告)号：US07155599B2
公开(公告)日：2006-12-26
申请号：US09750095
申请日：2000-12-29
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen
IPC分类号： G06F9/40
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3857
摘要： A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.
摘要翻译：公开了具有寄存器重命名结构和方法的处理器来恢复空闲列表。该处理器包括一个包括物理寄存器的物理寄存器文件。处理器还包括解码器，用于解码指示目的地逻辑寄存器的指令。处理器还包括寄存器分配表，以将目的地逻辑寄存器映射到所分配的物理寄存器。该处理器还包括一个包含旧字段和新字段的活动列表。旧字段至少包含一个从寄存器别名表中删除的物理寄存器。新的领域包括分配的物理寄存器。处理器还包括从活动列表中回收的未分配物理寄存器的空闲列表。

100. 发明授权

US07024542B2 System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions 失效
公开(公告)号：US07024542B2
公开(公告)日：2006-04-04
申请号：US10183096
申请日：2002-06-26
申请人： Guillermo Savransky , Ronny Ronen , Antonio Gonzalez
发明人： Guillermo Savransky , Ronny Ronen , Antonio Gonzalez
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. One method entails not performing an alias register to real register copying if the incoming instruction does not designate a real register. Another method entails delaying alias register to real register copying until the corresponding reorder buffer (ROB) entry is actually written to. Yet another method entails not performing an alias register to real register copying if the ROB entry is the same as the existing ROB entry. And, still another method entails further delaying or stalling the allocation of an ROB entry.

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