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91. 发明专利

JPS61278711A PULSE CONVERTING AND INTEGRATING DEVICE 失效
公开(公告)号：JPS61278711A
公开(公告)日：1986-12-09
申请号：JP12033085
申请日：1985-06-03
申请人： OSAKI ELECTRIC CO LTD
发明人： ISHIDOYA TORU
IPC分类号： G01D1/04 , G01R11/02 , G01R11/16
摘要： PURPOSE:To eliminate an error due to the fraction of pulse weight by setting and storing the pulse weight in a fraction, calculating a pulse whenever it is inputted and inputting a remainder arising at said calculation to the next calculation. CONSTITUTION:The pulse weight is set in a fraction by a pulse weight fraction setting device 5, and the set value is stored in pulse weight memories 12 and 13. A remainder memory 14 is installed, and the remainder below an effective digit, which arose in the previous calculation, is stored in it. Whenever the pulse is inputted, an arithmetic processing circuit 10 adds the pulse weight value stored in the memories 12 and 13 to the remainder stored in the remainder memory 14, and a counter 14 separates the effective digit value and integrates the value of an cumulative value memory 16. The remainder arising in the integration is stored in the remainder memory 14 by updating contents, and the operation is ready for the next pulse arrival.

92. 发明专利

JPS61260120A ELECTRONIC INTEGRATING INSTRUMENT 失效
公开(公告)号：JPS61260120A
公开(公告)日：1986-11-18
申请号：JP10244585
申请日：1985-05-14
申请人： OSAKI ELECTRIC CO LTD
发明人： FUJINUMA HIDEFUMI , UEDA YOSHINOBU
IPC分类号： G01R22/00 , G01D18/00 , G01R35/00
摘要： PURPOSE:To shorten a test time by counting a pulse signal for testing obtained from the intermediate frequency dividing step of a frequency converting circuit or a frequency dividing circuit for a prescribed time with a counter for testing. CONSTITUTION:Test electric power is supplied to an electric power detecting circuit 6 in a testing state. Further, a selecting signal (a) is inputted to a selecting signal input terminal ta. When the signal (a) is given to a control circuit 14, the circuit 14 first sends a gate closing signal (b) to a counter 10 for testing to close a gate incorporated in it. Then, the counter 10 is reset by a counter resetting signal (d). Then, a gate opening signal (e) is sent to the counter 10 to start the counting of the pulse signal for testing. Further, the circuit 14 transmits the counted value of the counter 10 to a latch circuit 11 by a data transmitting signal (c). Further, a data (h) from the circuit 11 is sent out from a data output terminal tb to a testing device by an output command signal (g). Accordingly, with the testing device, since a counting and arithmetic circuit is only required to read the data to which the pulse signal for testing is counted, a lot of instruments to be measured can be tested at high speed at a time.

93. 发明专利

JPS61198927A FREQUENCY SHIFT MODULATION SIGNAL INJECTING DEVICE UTILIZING COARSELY COUPLED TRANSFORMER 失效
公开(公告)号：JPS61198927A
公开(公告)日：1986-09-03
申请号：JP3759685
申请日：1985-02-28
申请人： KYUSHU DENKI SEIZO KK , OSAKI ELECTRIC CO LTD
发明人： KUDO TOMIHIRO , KUNITOMI NOBUYUKI
IPC分类号： H04B3/54 , H04B3/56
摘要： PURPOSE:To increase the transmission speed of a power line carrier supervisory control system and to decrease the effect of leakage magnetic flux by using a coarsely coupled transformer of closed magnetic path iron core structure with a gap so as to inject a signal in an FS carrier frequency to a power line. CONSTITUTION:A switching circuit 3 uses a signal from a control logic circuit 2 to switch transistors (TRs) T1, T2 thereby generating AC of mark and space frequencies. Capacitors C1, C2 are provided to the primary and secondary sides of the coarsely coupled transformer and the primary side is switched by the switching circuit 3 so as to generate mark and space signals subject to FS modulation. In the coarsely coupled transformer, windings are provided to the left/right legs of the E type iron core and the iron core has an air gap. The degree of coupling is adjusted by adjusting the air gap. Since the FS modulation system is adopted, the transmission speed is increased and since the closed magnetic path iron core is used, the leakage magnetic flux is decreased.

94. 发明专利

JPS61176874A METHOD FOR CHECKING FUNCTION OF ELECTRONIC TYPE ELECTRIC POWER MEASURING INSTRUMENT 失效
公开(公告)号：JPS61176874A
公开(公告)日：1986-08-08
申请号：JP1662285
申请日：1985-02-01
申请人： OSAKI ELECTRIC CO LTD
发明人： ISHIDOYA TORU , NAKAZATO ISAMU
IPC分类号： G01R35/04 , G01R21/06
摘要： PURPOSE:To display which part is under check and to find out easily a fault point by indicating the result of the check on a display part for measuring data of electric power. CONSTITUTION:The ROM contained in a control arithmetic circuit 13 is replaced with a test ROM and the RAM and non-volatile memory 15 contained in the circuit 13 are checked. For example, an on-peak apparent electric energy display part 23 is flickered if the result of the discrimination is negative. The circuit 13 calculates the square root of the sum of the square of the reference voltage data inputted from A/D conversion circuits 9, 10 and makes display by flickering, for example an off-peak apparent electric energy display part 25 if the calculated value is out of a specified range. The circuit flickers a present demand display part 27 if the result is acceptable. The outputs from an available power detecting circuit 5 and a reactive power detecting circuit 6 are inputted to the circuit 13 which calculates the available power value and reactive power value and displays the same on, for example, the apparent electric energy display parts 23, 25. The circuit determines the apparent power value and displays the same on, for example, the display part 27.

95. 发明专利

JPS61173189A PROGRAM TIME SWITCH 失效
公开(公告)号：JPS61173189A
公开(公告)日：1986-08-04
申请号：JP1359385
申请日：1985-01-29
申请人： OSAKI ELECTRIC CO LTD
发明人： HIRAMA MASAYOSHI , WATANABE SATORU
IPC分类号： G04G15/00
摘要： PURPOSE:To make possible the confirmation at a glance of the presence or absence of the load control of each day for a prescribed number of days by providing an array display means in which plural mark display parts display the presence or absence of the load control of the corresponding days. CONSTITUTION:The corresponding month and day are displayed on a number display part 5 when, for example, the position of a 'program' is selected to the position 'month and day' while an automatic operation mode is held selected by a set switch 2. The program number of the day is then displayed on a program number display part 6 and the schedules for one month are displayed by bars in one-day unit on a bar display part 7. The operator confirms the bar display of this time by viewing the index in the lower part. The confirmation at a glance of the presence or absence of the load control is thus made possible.

96. 发明专利

JPS61173188A PROGRAM TIME SWITCH 失效
公开(公告)号：JPS61173188A
公开(公告)日：1986-08-04
申请号：JP1359285
申请日：1985-01-29
申请人： OSAKI ELECTRIC CO LTD
发明人： HIRAMA MASAYOSHI , WATANABE SATORU
IPC分类号： G04G15/00
摘要： PURPOSE:To make possible the confirmation of the schedule contents of the day even during automatic operation by providing a display instruction means which can be used when a set mode is changed over to an automatic operation mode. CONSTITUTION:For example, a microprocessor 12 displays the present time on a number display part 5 and displays the set program number of the day on a program number display part 6 if the position of a 'program' is assumed to be selected while the automatic operation mode is held selected by a set switch. The program number can be thereby displayed as far as the position of the 'program' or 'time', etc. is held set by a display selector switch even while the automatic operation mode is set. The easy confirmation of the schedule contents of the day is thus made possible even during the automatic operation.

97. 发明专利

JPS60200175A MULTI-PHASE ELECTRONIC TYPE ELECTRIC WATTHOUR METER 失效
公开(公告)号：JPS60200175A
公开(公告)日：1985-10-09
申请号：JP5614784
申请日：1984-03-26
申请人： TOKYO ELECTRIC POWER CO , OSAKI ELECTRIC CO LTD
发明人： SHIMIZU KOUICHI
IPC分类号： G01R22/00 , G01R21/06
摘要： PURPOSE:To eliminate the mutual balance error between powers, by interchanging the connection relation of a resistor and a multiplier at every definite period and bringing a current value classified by phases flowed into an imaginary earth point to the average value of the current obtained by converting the output voltage of a multiplier classified by phases by a resistor. CONSTITUTION:Because analogue switches 10, 11 are turned ON and analogue switches 9, 12 are turned OFF for a definite period when the output Q of T-type FF8 is a low level and the output Q thereof is a high level, the output voltage ep1 of a multiplier circuit 4 is applied to a resistor R2 and the output voltage ep2 of a multiplier circuit 5 is applied to a resistor R1 and both voltages are converted to currents to receive current synthesis at the imaginary earth point of a current-frequency converter circuit 6. Because the resistors R1, R2 connected to multipliers 4, 5 are interchanged at every definite period and interchanging is repeated, the output voltage ep1 of the multiplier 4 is successively converted by the resistors R1, R2 and the current inputted to the current- frequency converter circuit 6 and the output voltage ep2 of the multiplier 5 are successively converted by the resistors R1, R2. By this mechanism, the mutual balance error between powers can be brought to zero even if there is the relative error between the resistors R1, R2.

98. 发明专利

JPS6014309B2 失效
公开(公告)号：JPS6014309B2
公开(公告)日：1985-04-12
申请号：JP12987280
申请日：1980-09-17
申请人： OSAKI ELECTRIC CO LTD
发明人： UEDA YOSHINOBU
IPC分类号： G01R22/00 , G01D4/00 , G01R11/57 , G01R21/00

99. 发明专利

JPS6062737A PHASE PULSE SIGNAL SYNCHRONIZING METHOD 失效
公开(公告)号：JPS6062737A
公开(公告)日：1985-04-10
申请号：JP17169283
申请日：1983-09-17
申请人： OSAKI ELECTRIC CO LTD
发明人： TAKAGI MASATOSHI , ITOU TOSHIHIKO
IPC分类号： H02J13/00 , H04B3/54
摘要： PURPOSE:To decrease the transmission time of a phase pulse synchronizing signal by injecting a phase pulse synchronizing signal to all channels at the synchronizing mode and averaging a subtracted value between the channels. CONSTITUTION:The same phase pulse synchronizing signal 9 as the phase pulse signal is injected to all the channels CH1-CH10 at the signal cycle 3 and no phase pulse synchronizing signal 9 is injected at the noise detection cycle 4. The reception side separates a reception waveform 12 of the phase pulse synchronizing signal including noises from an ANC voltage wave of the reception cycle 3 and stores a digital value D3 in a memory. A noise waveform 16 is detected at the noise detection cycle 4, the waveform is converted into a digital value D4 and stored in the memory. Then the D4 is subtracted from the digital value D3 and the subtracted value is subjected to arithmetic average among the channels CH1-CH10. The result is stored for a prescribed number of times, the preceding average value is compared, and when the average value is decreased less han the preceding average value, it is descriminated that the synchronism is finished.

100. 发明专利

JPS59139830A Phase pulse signal oscillating circuit 失效
标题翻译：相脉冲信号振荡电路
公开(公告)号：JPS59139830A
公开(公告)日：1984-08-10
申请号：JP1232683
申请日：1983-01-28
申请人： Osaki Electric Co Ltd
发明人： TAKAGI MASATOSHI , FUKUSHIMA MITSUAKI , KATSURA SHIGENORI , KOMAZAWA SATOSHI
IPC分类号： H03B11/00 , H02J13/00 , H03K3/02 , H04B3/44 , H04B3/54
CPC分类号： Y02E60/7892 , Y04S40/146

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