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    • 92. 发明授权
    • Plasma display panel and driving method therefor
    • 等离子显示面板及其驱动方法
    • US07492331B2
    • 2009-02-17
    • US10896012
    • 2004-07-22
    • Seung-Hun ChaeWoo-Joon ChungJin-Sung KimKyoung-Ho Kang
    • Seung-Hun ChaeWoo-Joon ChungJin-Sung KimKyoung-Ho Kang
    • G09G3/28
    • G09G3/2022G09G3/2927G09G2320/0276G09G2360/16
    • Apparatus and method for a plasma display panel (PDP) for controlling power on external video data and generating power control data into N subfields to represent grays is provided having a plasma panel including a plurality of address electrodes, scan electrodes and sustain electrodes arranged in pairs with the address electrodes, a controller for performing power control on the video data to generate N subfields, generating subfield data and sustain pulse information corresponding to the respective subfields, and outputting a floating control signal for controlling a floating time according to the sustain pulse information, an address data driver for applying a voltage that corresponds to the subfield data to the address electrode, a sustain electrode driver for applying a voltage to the sustain electrode according to the sustain pulse information output by the controller, and a scan electrode driver for controlling the floating time according to the floating control signal, and applying a voltage to the scan electrode according to the sustain pulse information.
    • 提供了一种等离子体显示面板(PDP)的装置和方法,用于控制外部视频数据的电力并将功率控制数据生成到N个子场中以表示灰度,其具有包括成对布置的多个地址电极,扫描电极和维持电极的等离子体面板 与地址电极相连的控制器,用于对视频数据执行功率控制以产生N个子场,产生子场数据并维持对应于各个子场的脉冲信息,并根据维持脉冲信息输出用于控制浮动时间的浮动控制信号 ,用于将对应于子场数据的电压施加到寻址电极的地址数据驱动器,根据由控制器输出的维持脉冲信息向维持电极施加电压的维持电极驱动器,以及用于控制的扫描电极驱动器 浮动时间根据浮动控制信号,并应用 根据维持脉冲信息对扫描电极施加电压。
    • 93. 发明授权
    • Resonant inverter exhibiting depressed duty variation
    • 谐振逆变器表现出降低的负载变化
    • US07492141B2
    • 2009-02-17
    • US11784162
    • 2007-04-04
    • Jong-Tae HwangMoon-Sang JungDong-Hwan KimJin-Sung Kim
    • Jong-Tae HwangMoon-Sang JungDong-Hwan KimJin-Sung Kim
    • G05F1/40G05F1/56
    • H02M3/3376H02M2001/0058Y02B70/1433Y02B70/1491
    • A resonant inverter includes a first driver and a second driver for driving a first and second switching devices, respectively, a dead time generator for generating a first drive signal and a second drive signal respectively, a current-controlled oscillator for supplying, to the dead time generator, an output clock having a frequency determined based on a first current input to the current-controlled oscillator, and a current mirror for supplying the first current to the current-controlled oscillator in an amount proportional to a second current flowing through an external resistor. The current mirror includes a track/hold circuit, to supply the second current in an amount equal to an amount of the second current supplied before a variation in the amount of the second current, during a transition of an output signal between the first and second switching devices.
    • 谐振逆变器包括分别用于驱动第一和第二开关装置的第一驱动器和第二驱动器,分别用于产生第一驱动信号和第二驱动信号的死区时间发生器,用于向死人提供电流控制振荡器 时间发生器,具有基于对电流控制振荡器的第一电流输入而确定的频率的输出时钟以及用于以与流过外部电流的第二电流成比例的量向电流控制振荡器提供第一电流的电流镜 电阻。 电流镜包括跟踪/保持电路,以在第一和第二电平之间的输出信号的转变期间提供等于第二电流量的变化之前提供的第二电流的量的量的第二电流 开关器件。
    • 95. 发明授权
    • Driving apparatus of plasma display panel
    • 等离子显示面板驱动装置
    • US07460089B2
    • 2008-12-02
    • US11075868
    • 2005-03-10
    • Jin-Sung KimWoo-Joon ChungSeung-Hun Chae
    • Jin-Sung KimWoo-Joon ChungSeung-Hun Chae
    • G09G3/28
    • H01J11/10G09G3/2927G09G3/293G09G3/296G09G2320/0228
    • A driving apparatus of a plasma display panel. In a scan electrode driving circuit, a drain of a first transistor is coupled to a scan electrode, and a driver of the first transistor is coupled to the gate and a source of the first transistor. During a reset period, the driver turns on the first transistor and reduces a voltage at a scan electrode and then turns off the first transistor so as to gradually reduce the voltage of the scan electrode by floating the scan electrode. Further, a selecting voltage may be applied to the scan electrode by turning on the first and second transistors during an address period. Thus, the transistor used during the reset period may be used in the address period.
    • 等离子体显示面板的驱动装置。 在扫描电极驱动电路中,第一晶体管的漏极耦合到扫描电极,第一晶体管的驱动器耦合到第一晶体管的栅极和源极。 在复位期间,驱动器接通第一晶体管并降低扫描电极的电压,然后关断第一晶体管,从而通过浮置扫描电极来逐渐降低扫描电极的电压。 此外,通过在寻址周期期间接通第一和第二晶体管,可以向扫描电极施加选择电压。 因此,在复位周期期间使用的晶体管可以在寻址周期中使用。
    • 96. 发明授权
    • Method of driving discharge display panel by address-display mixing
    • 通过地址显示混合驱动放电显示面板的方法
    • US07372434B2
    • 2008-05-13
    • US10962708
    • 2004-10-13
    • Kyoung-Ho KangWoo-Joon ChungJin-Sung KimSeung-Hun Chae
    • Kyoung-Ho KangWoo-Joon ChungJin-Sung KimSeung-Hun Chae
    • G09G3/28
    • G09G3/294G09G3/2932G09G3/2935G09G2310/0216G09G2310/0218G09G2320/0228
    • In a method of driving a discharge display panel, each subfield may include a first address period, a first display-sustain period, a second address period, and a second display-sustain period. In the first address period, a predetermined wall voltage may be generated in display cells selected from the display cells of the first display electrode-line pair group. In the first display-sustain period, display-sustain discharge may occur during a time proportional to a gray scale weight of each of the subfields in the selected display cells of the display cells of the first display electrode-line pair group when the first address period has elapsed. In the second address period, a predetermined wall voltage may be generated in display cells selected from the display cells of the second display electrode-line pair group when the first display-sustain period has elapsed. In the second display-sustain period, display-sustain discharge may occur during a time proportional to a gray scale weight of each of the subfields in the selected display cells of the display cells of the first and second display electrode-line pair groups when the second address period has elapsed.
    • 在驱动放电显示面板的方法中,每个子场可以包括第一寻址周期,第一显示维持周期,第二寻址周期和第二显示维持周期。 在第一寻址期间,可以在从第一显示电极线对组的显示单元中选择的显示单元中产生预定的壁电压。 在第一显示维持期间,当与第一显示电极线对组的显示单元的所选择的显示单元中的每个子场的灰度权重成比例时,显示维持放电可能发生在第一显示电极线对组 时间过去了 在第二寻址期间,当经过第一显示维持期间时,可以在从第二显示电极线对组的显示单元中选择的显示单元中产生预定的壁电压。 在第二显示维持期间,当与第一和第二显示电极线对组的显示单元的所选择的显示单元中的每个子场的灰度权重成比例的时间期间,显示维持放电可以发生在 第二个地址周期已过。
    • 99. 发明申请
    • Logic circuit for high-side gate driver
    • 高边栅驱动逻辑电路
    • US20070296462A1
    • 2007-12-27
    • US11800198
    • 2007-05-04
    • Jong-Tae HwangMoon-Sang JungJin-Sung KimDong-Hwan Kim
    • Jong-Tae HwangMoon-Sang JungJin-Sung KimDong-Hwan Kim
    • H03K19/0175
    • H03K19/018521
    • A logic circuit for high-side gate driver includes a p-MOSFET array connected to a first voltage source, an n-MOSFET array connected to a second voltage source, and a resistor arranged between the p-MOSFET array and the n-MOSFET array, wherein a first node between the resistor and at least one of the p-MOSFETs in the p-MOSFET array is connected to a first output terminal, and a second node between the resistor and at least one of the n-MOSFETs in the n-MOSFET array is connected to a second output terminal. An additional logic circuit can include a second p-MOSFET array, a second n-MOSFET array, and a second resistor between the second p-MOSFET array and the second n-MOSFET array, where an output signal from an output terminal between the first resistor and the first n-MOSFET array is fed back to the second p-MOSFET array and the second n-MOSFET array, and an output signal from an output terminal between the second resistor and the second n-MOSFET array is fed back to the first p-MOSFET array and the first n-MOSFET array.
    • 用于高侧栅极驱动器的逻辑电路包括连接到第一电压源的p-MOSFET阵列,连接到第二电压源的n-MOSFET阵列和布置在p-MOSFET阵列和n-MOSFET阵列之间的电阻器 ,其中所述电阻器和所述p-MOSFET阵列中的至少一个p-MOSFET之间的第一节点连接到第一输出端子,并且所述电阻器和所述n个中的至少一个n-MOSFET的第二节点 -MOSFET阵列连接到第二输出端。 附加的逻辑电路可以包括第二p-MOSFET阵列,第二n-MOSFET阵列和在第二p-MOSFET阵列和第二n-MOSFET阵列之间的第二电阻,其中来自第一 电阻器和第一n-MOSFET阵列被反馈到第二p-MOSFET阵列和第二n-MOSFET阵列,并且来自第二电阻器和第二n-MOSFET阵列之间的输出端的输出信号被反馈到 第一个p-MOSFET阵列和第一个n-MOSFET阵列。
    • 100. 发明授权
    • Plasma display panel and apparatus and method for driving the same
    • 等离子显示面板及其驱动方法
    • US07274343B2
    • 2007-09-25
    • US10445274
    • 2003-05-23
    • Jun-Hyung KimJin-Sung KimMyeong-Seob SoNam-Sung Jung
    • Jun-Hyung KimJin-Sung KimMyeong-Seob SoNam-Sung Jung
    • G09G3/10G09G3/28
    • G09G3/2965G09G3/2932G09G2300/0408G09G2310/06G09G2330/024G09G2330/06
    • A PDP address driver circuit includes: an inductor coupled to a conductive pattern. A first current applier applyies a current of a first direction to the inductor and the conductive pattern while sustaining a panel capacitor at an address voltage. A discharger generates a resonance between the inductor and the panel capacitor to discharge the panel capacitor to 0V, while the current of the first direction flows to the inductor and the conductive pattern. A second current applier applyies a current of a second direction to the inductor and the conductive pattern while sustaining the panel capacitor at 0V. A charger generates a resonance between the inductor and the panel capacitor to charge the panel capacitor to the address voltage, while the current of the second direction flows to the inductor and the conductive pattern.
    • PDP地址驱动器电路包括:耦合到导电图案的电感器。 第一个当前的施加器将电流和第一方向施加到电感器和导电图案,同时在寻址电压下维持面板电容器。 放电器在电感器和面板电容器之间产生谐振,以将面板电容器放电到0V,而第一方向的电流流向电感器和导电图案。 第二个当前的施加器将电流和第二方向应用于电感器和导电图案,同时将面板电容器维持在0V。 充电器在电感器和面板电容器之间产生谐振,以将面板电容器充电到寻址电压,而第二方向的电流流向电感器和导电图案。