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91. 发明授权

US07438495B2 Sideward clipping apparatus 失效
标题翻译：侧向裁剪装置
公开(公告)号：US07438495B2
公开(公告)日：2008-10-21
申请号：US11245161
申请日：2005-10-07
申请人： Chin-Wen Chou , Hong-Yi Lee
发明人： Chin-Wen Chou , Hong-Yi Lee
IPC分类号： B25G3/18 , F16B21/00 , F16D1/00
CPC分类号： B25G3/18 , Y10T403/591 , Y10T403/595
摘要： A sideward clipping apparatus aims to clip and release an article through double-depressing actions in cyclic operations. It has a sliding member which includes an upper clipping portion and a lower clipping portion that are coupled through a first base and a second base. The lower clipping portion synchronously drives the upper clipping portion through the first base at an initial force receiving state to form a first fan moving track. The lower clipping portion is in contact with the sliding member and moved vertically to a second position under the force to drive the upper clipping portion through the second base to form a second fan moving track. Thereby the upper clipping portion and the lower clipping portion form a clipping space when the sliding member is moved to the second position to accurately clip the article.
摘要翻译：侧向裁剪装置旨在通过循环操作中的双击动作剪辑和释放物品。其具有滑动构件，其包括通过第一基座和第二基座联接的上夹持部分和下夹持部分。下夹具部分在初始力接收状态下同步地驱动上夹持部分穿过第一基座以形成第一扇形移动轨迹。下夹紧部分与滑动构件接触并且在力作用下垂直移动到第二位置，以通过第二底座驱动上夹持部分以形成第二扇形移动轨道。因此，当滑动构件移动到第二位置时，上夹持部分和下夹持部分形成夹紧空间，以精确地夹住制品。

92. 发明申请

US20080189518A1 PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES 有权
标题翻译：具有双读模式的处理器指令高速缓存
公开(公告)号：US20080189518A1
公开(公告)日：2008-08-07
申请号：US12061296
申请日：2008-04-02
申请人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
发明人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
IPC分类号： G06F9/312
CPC分类号： G06F12/0882 , G06F9/30054 , G06F9/30058 , G06F9/3804 , G06F9/3844 , G11C7/06 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/12 , G11C7/22 , G11C2207/2245 , G11C2207/2281 , Y02D10/13
摘要： A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.
摘要翻译：处理器包括具有阵列，字线和位线的高速缓冲存储器。控制模块在访问周期期间访问阵列的单元以访问存储在高速缓冲存储器中的指令。控制模块执行第一离散读取和第一顺序读取之一以访问连接到第一字线的阵列的第一组单元中的指令，并且选择性地执行第二离散读取和第二顺序读取之一在分支指令上访问连接到第二字线的阵列的第二组单元格中的指令。第二个字线与第一个字线不同。

93. 发明申请

US20080143413A1 PROGRAMMABLE DELAY CIRCUIT 有权
标题翻译：可编程延时电路
公开(公告)号：US20080143413A1
公开(公告)日：2008-06-19
申请号：US11738523
申请日：2007-04-23
申请人： Hong-Yi Huang , Shiun-Dian Jan , Yuan-Hua Chu
发明人： Hong-Yi Huang , Shiun-Dian Jan , Yuan-Hua Chu
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.
摘要翻译：提供了包括第一反相器，第二反相器，可变电阻单元和可变电容单元的可编程延迟电路。第一反相器接收正相接收信号，并通过反相输出信号线发送反相输出信号。第二反相器接收反相接收信号，并通过正相输出信号线发送正相输出信号。可变电阻单元根据延迟控制代码中的M位调节反相输出信号线和正相输出信号线之间的等效电阻。可变电容单元根据延迟控制代码中的N位来调节反相输出信号线和正相输出信号线之间的等效电容。

94. 发明申请

US20070030041A1 DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner 有权
公开(公告)号：US20070030041A1
公开(公告)日：2007-02-08
申请号：US11194628
申请日：2005-08-02
申请人： Hong-Yi Huang , Jian-Hong Shen , Yuan-Hua Chu
发明人： Hong-Yi Huang , Jian-Hong Shen , Yuan-Hua Chu
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03K5/133 , H03K2005/00026 , H03K2005/00052 , H03L7/0812 , H03L7/0891
摘要： A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

95. 发明申请

US20060212687A1 Dual thread processor 有权
标题翻译：双线程处理器
公开(公告)号：US20060212687A1
公开(公告)日：2006-09-21
申请号：US11084364
申请日：2005-03-18
申请人： Hong-Yi Chen , Sehat Sutardja
发明人： Hong-Yi Chen , Sehat Sutardja
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3861 , G06F9/3867
摘要： A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.
摘要翻译：提供了流水线处理器架构，处理器和方法。在一个实现中，提供了一种处理器，其包括指令获取单元，其可操作以获取与多个处理器线程相关联的指令，响应于指令提取单元的解码器，响应于解码器的发布逻辑，以及包括多个对应于多个处理器线程的存储体。每个存储体可操作地存储与相应处理器线程相关联的数据。处理器可以包括与多个处理器线程中的每一个对应的一组寄存器。一组中的每个寄存器位于处理器的流水线阶段之前或之后。

96. 发明申请

US20050253630A1 Dual-modulus prescaler using double edge triggered D-flip-flops 审中-公开
标题翻译：双模预分频器采用双边沿触发D触发器
公开(公告)号：US20050253630A1
公开(公告)日：2005-11-17
申请号：US10842569
申请日：2004-05-11
申请人： Hong-Yi Huang , Sheng-Feng Ho , Hsuan-Yi Su
发明人： Hong-Yi Huang , Sheng-Feng Ho , Hsuan-Yi Su
IPC分类号： H03K21/00 , H03K23/66 , H03K23/68
CPC分类号： H03K23/68 , H03K23/667
摘要： The present invention provides one dual-modulus prescaler using double edge triggered D-flip-flops. The dual-modulus prescaler comprises one double edge triggered synchronous block, one asynchronous block, and one combination logic block. The double edge triggered synchronous block is used to receive an input signal and a divisor selection signal from the combination logic block, and output a synchronous block output signal to the asynchronous block. The asynchronous block is used to receive the synchronous block output signal and output a plurality of signals to the combination logic block. One of the output signals of the asynchronous block is the output signal of the dual-modulus prescaler. The combination logic block is used to receive all the output signals of the asynchronous block and a modulus selection signal. Then, the combination logic block outputs the divisor selection signal and feeds it back to the double edge triggered synchronous block. The double edge triggered synchronous blockish composed of a plurality of D-flip-flops.
摘要翻译：本发明提供了一种使用双边沿触发D触发器的双模预分频器。双模预分频器包括一个双边沿触发同步块，一个异步块和一个组合逻辑块。双边沿触发同步块用于从组合逻辑块接收输入信号和除数选择信号，并将同步块输出信号输出到异步块。异步块用于接收同步块输出信号并将多个信号输出到组合逻辑块。异步块的输出信号之一是双模预分频器的输出信号。组合逻辑块用于接收异步块的所有输出信号和模数选择信号。然后，组合逻辑块输出除数选择信号并将其馈送回双边缘触发同步块。由双重触发器组成的双边沿触发同步阻塞。

97. 发明申请

US20050095537A1 Method and system of controlling dummy dispense 有权
标题翻译：控制虚假分配的方法和系统
公开(公告)号：US20050095537A1
公开(公告)日：2005-05-05
申请号：US10696300
申请日：2003-10-29
申请人： Hong-Yi Wu , Chih-Jung Weng , Chung-Cheng Ni , Yi-Hsin Yu
发明人： Hong-Yi Wu , Chih-Jung Weng , Chung-Cheng Ni , Yi-Hsin Yu
IPC分类号： G03F7/00 , G03F7/16 , G03F7/20 , G05B19/43 , H01L21/00
CPC分类号： G03F7/162 , G03F7/16 , H01L21/6715
摘要： A dummy dispense of liquid is controlled by recording a time at which a substrate is processed; recording a time at which a liquid is dispensed; comparing the time at which the substrate is processed and the time at which the liquid is dispensed to generate a dummy dispense signal when a dummy dispense is required. A system for controlling dummy dispense of liquid includes at least one information storage device storing a time at which a substrate is processed and a time at which a liquid is dispensed. At least one processor compares the time at which the substrate is processed and the time at which the liquid is dispensed to determine whether a dummy dispense is required.
摘要翻译：通过记录处理基板的时间来控制液体的虚拟分配; 记录液体分配的时间; 比较基板被处理的时间和分配液体的时间，以便在需要虚拟分配时产生虚拟分配信号。用于控制液体的虚拟分配的系统包括至少一个存储基板被处理的时间和分配液体的时间的信息存储装置。至少一个处理器比较基板被处理的时间和分配液体的时间，以确定是否需要虚拟分配。

98. 发明授权

US06850492B2 Method and system for enabling a route and flow table update in a distributed routing platform 有权
标题翻译：在分布式路由平台中启用路由和流表更新的方法和系统
公开(公告)号：US06850492B2
公开(公告)日：2005-02-01
申请号：US10302709
申请日：2002-11-22
申请人： Vijay K. Chander , Atul B. Mahamuni , Ramkumar Sankar , Sreeram Iyer , Henry Hong-Yi Tzeng
发明人： Vijay K. Chander , Atul B. Mahamuni , Ramkumar Sankar , Sreeram Iyer , Henry Hong-Yi Tzeng
IPC分类号： H04J3/14 , H04L12/28 , H04L12/56
CPC分类号： H04L45/583 , H04L45/00 , H04L45/58 , H04L45/60 , Y10S707/99938
摘要： A system and method is directed to updating a route table in a distributed routing platform, thereby enabling multiple routing protocols to be executed on different routing modules. A slave route distributor on one routing module is configured to receive a route from a local route table and flow manager. The slave route distributor communicates the route to a master route distributor on another routing module by way of an inter process communications protocol. The master route distributor provides the route to its local route table and flow manager, where a determination is made whether the route is a best route. If the route is a best route, the master route distributor updates its external routing table. The master route distributor also distributes the route to another slave route distributor on yet another routing module, where the route enables an update to a remote routing protocol, and routing table.
摘要翻译：系统和方法旨在更新分布式路由平台中的路由表，从而使得能够在不同的路由模块上执行多个路由协议。一个路由模块上的从属路由分配器被配置为从本地路由表和流管理器接收路由。从路由分配器通过进程间通信协议将路由传递到另一路由模块上的主路由分发器。主路由分配器提供到其本地路由表和流管理器的路由，其中确定路由是否是最佳路由。如果路由是最佳路由，则主路由分发器更新其外部路由表。主路由分配器还将路由分配到另一路由模块上的另一个从属路由分发器，其中该路由能够更新远程路由协议和路由表。

99. 发明授权

US06704320B1 Dynamic algorithm for determining a shortest path tree between network nodes 失效
标题翻译：用于确定网络节点之间最短路径树的动态算法
公开(公告)号：US06704320B1
公开(公告)日：2004-03-09
申请号：US09275591
申请日：1999-03-24
申请人： Paolo Narvaez , Kai-Yeung Siu , Hong-Yi Tzeng
发明人： Paolo Narvaez , Kai-Yeung Siu , Hong-Yi Tzeng
IPC分类号： H04L1228
CPC分类号： H04L45/02 , H04L45/48
摘要： A dynamic shortest path tree (SPT) algorithm for a router determines a new SPT for a root node in response to a link-state or other network topology change. The dynamic SPT algorithm determines the new SPT as an optimization problem in a linear programming framework based in an existing SPT in the router. The dynamic SPT algorithm emulates maximum decrement of a ball and string model by iteratively selecting nodes of the existing SPT for consideration and update of parent node, child nodes, and distance attributes based on the maximum decrement. For the maximum decrement, a node in the existing SPT is selected by each iteration based on the greatest potential decrease (or least increase) in its distance attribute. The ball and string model that may be employed for the dynamic SPT algorithm represents a network of nodes and links with a ball representing a node and a string representing a link or edge. The length of a string is defined by its link's weight. The set of strings connecting the balls defines a path between the root node and a particular node. The shortest path is the path defined by the strings from a root node to a particular node that are tight. For the dynamic SPT algorithm, an increase (or decrease) in an edge weight in an existing SPT corresponds to a lengthening (or shortening) of a string. By sequentially pulling balls away in a single direction from the ball of the root node, the new SPT becomes defined by the balls and tight strings.
摘要翻译：用于路由器的动态最短路径树（SPT）算法根据链路状态或其他网络拓扑变化确定根节点的新SPT。动态SPT算法将新的SPT确定为基于路由器中现有SPT的线性规划框架中的优化问题。动态SPT算法通过迭代地选择现有SPT的节点来模拟球和串模型的最大减量，以便基于最大减量来考虑和更新父节点，子节点和距离属性。对于最大减量，根据其距离属性中的最大潜在减少（或最小增加），通过每次迭代选择现有SPT中的节点。可用于动态SPT算法的球和弦模型表示节点的网络和与表示节点的球的链接和表示链接或边缘的字符串。字符串的长度由其链接的权重定义。连接球的一组字符串定义了根节点和特定节点之间的路径。最短路径是由根节点到特定节点的字符串定义的路径。对于动态SPT算法，现有SPT中边缘权重的增加（或减小）对应于字符串的延长（或缩短）。通过从根节点的球顺序地将球从单个方向拉出，新的SPT由球和紧密的弦组成。

100. 发明授权

US06456120B1 Capacitor-coupling differential logic circuit 有权
标题翻译：电容耦合差分逻辑电路
公开(公告)号：US06456120B1
公开(公告)日：2002-09-24
申请号：US09707796
申请日：2000-11-08
申请人： Hong-Yi Huang
发明人： Hong-Yi Huang
IPC分类号： H03K1920
CPC分类号： H03K3/356139 , G11C7/065
摘要： A capacitor-coupling differential logic circuit handling the output of a differential circuit using coupling capacitors and sense amplifier. The coupling capacitors can couple a control signal to the corresponding internal terminal, i.e., the output terminal of the differential circuit. During evaluation, the differential circuit generates a voltage difference on the internal signal of the internal terminal according to the input signal and the predetermined logic operation. The sense amplifier is used to amplify and output the voltage difference on the internal; signal at the internal terminal.
摘要翻译：电容耦合差分逻辑电路，使用耦合电容和读出放大器处理差分电路的输出。耦合电容器可以将控制信号耦合到对应的内部端子，即差分电路的输出端子。在评估期间，差分电路根据输入信号和预定的逻辑运算产生对内部端子的内部信号的电压差。读出放大器用于放大和输出内部的电压差; 信号在内部终端。

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