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    • 94. 发明专利
    • DE19701262C2
    • 2001-09-27
    • DE19701262
    • 1997-01-17
    • ALLEGRO MICROSYSTEMS INC
    • MOODY KRISTANN LVIG RAVISCHELLER P KARLTOWNE JAY MTU TERI L
    • G01B7/00G01D3/02G01D5/14G01D5/244G01D5/245G01V3/08H03K17/95H03M1/30G01P3/487G01R33/07
    • A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. Vsig is applied to the input of a signal-manipulating circuit that generates a proximity- detector binary output voltage, Vout, having transitions of one direction each time a predetermined point is reached in Vsig. A digitally gain-controlled gain amplifier is connected to the Hall element. A comparator circuit generates a binary signal Vbig (or Vtoobig) that changes from one to another binary level each time that Vsig exceeds a DC target voltage, VTG. The AGC circuit senses and counts gain counter excursions of one polarity in Vsig, and produces a binary count output signal at the input of the gain amplifier at each of the counted excursions in Vsig, incrementally changing the transducer gain in the direction to bring the peaks in Vsig to just below the target value TTG. This AGC feature prevents saturating the amplifier and quickly renders a Vsig of essentially constant amplitude so that either the peak excursion values or predetermined threshold levels in Vsig, at which transitions in the proximity detector output voltage Vout are caused to occur, provide greater accuracy and stability in the correlation between detection-approach and -withdrawal distances and transitions in Vout.
    • 96. 发明专利
    • FR2734913B1
    • 2000-06-02
    • FR9606667
    • 1996-05-30
    • ALLEGRO MICROSYSTEMS INC
    • ENGEL RAYMOND WGILBERT PETER JVIG RAVITU TERICLAPP TERRY
    • G01P3/488G01B7/00G01D5/14G01D5/245G01D11/24G01P3/487G01V13/00G01V3/08G01B7/15
    • This invention is a magnetic-field sensor assembly comprising a preformed housing shell having a first end which includes an opening, and a second end which includes a window and having a cylindrical shape with a flattened portion to produce a truncated circular cross-section, a sensor package including an integrated-circuit magnetic-field-sensor chip encapsulated in a protective body with first and second opposite and mutually parallel faces and a plurality of integral conductive leads, each lead having a proximal portion, a distal portion, and a central portion, the proximal portion of each of said plurality of leads extending from said body, the central portion of said plurality of leads extending away from the body and positioned substantially normal the faces of the body, said sensor-package body being positioned in said housing shell part way through said window with said one body face extending outwardly from said housing shell and with said lead distal portions extending from said housing shell through said opening, a magnet having a first end and a second end and positioned in said housing shell with said first end adjacent to said second sensor-package body face, and an endcap adapted to close said opening in said housing shell.
    • 98. 发明专利
    • DE19701262A1
    • 1997-07-24
    • DE19701262
    • 1997-01-17
    • ALLEGRO MICROSYSTEMS INC
    • MOODY KRISTANN LVIG RAVISCHELLER P KARLTOWNE JAY MTU TERI L
    • G01B7/00G01D3/02G01D5/14G01D5/244G01D5/245G01V3/08H03K17/95H03M1/30G01P3/487G01R33/07
    • A magnetic-field-to-voltage transducer includes a Hall element and a digitally gain-controlled Hall-voltage amplifier that produces an analog voltage Vsig having excursions of one polarity corresponding to the passing of magnetic articles. Vsig is applied to the input of a signal-manipulating circuit that generates a proximity- detector binary output voltage, Vout, having transitions of one direction each time a predetermined point is reached in Vsig. A digitally gain-controlled gain amplifier is connected to the Hall element. A comparator circuit generates a binary signal Vbig (or Vtoobig) that changes from one to another binary level each time that Vsig exceeds a DC target voltage, VTG. The AGC circuit senses and counts gain counter excursions of one polarity in Vsig, and produces a binary count output signal at the input of the gain amplifier at each of the counted excursions in Vsig, incrementally changing the transducer gain in the direction to bring the peaks in Vsig to just below the target value TTG. This AGC feature prevents saturating the amplifier and quickly renders a Vsig of essentially constant amplitude so that either the peak excursion values or predetermined threshold levels in Vsig, at which transitions in the proximity detector output voltage Vout are caused to occur, provide greater accuracy and stability in the correlation between detection-approach and -withdrawal distances and transitions in Vout.
    • 99. 发明专利
    • DE19650184A1
    • 1997-06-12
    • DE19650184
    • 1996-12-04
    • ALLEGRO MICROSYSTEMS INC
    • BILOTTI ALBERTOMONREAL GERARDO
    • G01D5/14G01R15/20G01R33/07G11C27/02H01L43/06H03K17/90H03F15/00
    • A chopped Hall sensor includes a Hall-element switching circuit of the kind in which a Hall element has two pairs of diagonally opposite Hall contacts which are alternately connected to a pair of DC supply conductors and to a pair of Hall-stitching-circuit output conductors for alternately, during phase phi 1 and n phi 1 of a first clock signal, switching the Hall exciting current from flow in one to another direction through the Hall element. A linear analog double-differential Hall-voltage amplifier has an input connected to the output of the Hall switching-circuit. A sample-and-hold circuit is comprised of first and second elemental sample-and-hold circuits (ESHCs) with inputs connected respectively to the two Hall-voltage differential-amplifier outputs. The first and second ESHCs are respectively clocked, by second and third clock signals, to the sample Hall voltage signal only during phases phi 2 and phi 3 and to hold the sample signal during phases n phi 2 and n phi 3 respectively, where phi 2 and phi 3 occur respectively during a mid portion of phases phi 1 and n phi 1. Two inputs of a summer circuit are connected respectively to the outputs of the first and second ESHCs. A third and fourth ESHC may be added to form a crossed-polarity full-differential sample-and-hold circuit. The Hall voltage amplifier may include a clocked noise blanking circuit for reducing the differential-gain of the amplifier only during a time span encompassing each phase transition in the first clock signal.
    • 100. 发明专利
    • Detection of passing magnetic articles at speeds down to zero
    • GB9700984D0
    • 1997-03-05
    • GB9700984
    • 1997-01-17
    • ALLEGRO MICROSYSTEMS INC
    • G01B7/00G01D5/14G01D5/244G01D5/245G01V3/08H03K17/95
    • In a proximity-detector, a Hall transducer produces a signal Vsig. Two counters, P-counter and N-counter count pulses from a clock and produce count signals respectively to two DACs, PDAC and NDAC. The DACs output signals track and hold, respectively, the positive pulses and negative pulses in Vsig. These output signals are compared with Vsig to produce a proximity-detector binary output voltage Vout that becomes high when a tracking voltage VDAC-P produced by PDAC rises to each peak positive voltage Vpk in Vsig, and that becomes low when a tracking voltage VDAC-P falls to each peak negative voltage in Vsig. The peak VDAC-P is held until Vsig drops by a fixed amount below Vpk to produce an output pulse that resets the counter connected to PDAC at a time shortly following the actual peak in Vsig. Similarly, the peak VDAC-N is held until Vsig rises a fixed amount above VDAC-N to produce an output pulse that resets the counter connected to NDAC. The N-counter is reset at tnpk by the negative-peak indicating signal VNcomp and is enabled at tppk by the positive-peak indicating signal VPcomp, while the P-counter reset by the positive peak indicating signal VPcomp and enabled by VNcomp. This proximity detector detects articles passing at rates down to zero.