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1. 发明授权

US08482991B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08482991B2
公开(公告)日：2013-07-09
申请号：US13600271
申请日：2012-08-31
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C7/1078
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
摘要翻译：在对存储器单元进行的写入操作的指令的接收之后，数据输入缓冲器从非活动状态改变为活动状态。输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而使其通过电流流动并接收信号而进入激活状态，同时紧随着小的变化小振幅信号。由于只有当提供了对存储器单元的写操作指令时，输入缓冲器才进入活动状态，所以在提供指令之前预先使输入缓冲器无效，从而减少浪费的功耗。在另一方面，通过在从写入命令发布到下一个命令发布的时间段内从主动状态变为非活动状态来降低功耗。

2. 发明申请

WO2021034431A8 METHODS FOR PROVIDING DEVICE STATUS IN RESPONSE TO READ COMMANDS DIRECTED TO WRITE-ONLY MODE REGISTER BITS AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开
公开(公告)号：WO2021034431A8
公开(公告)日：2021-02-25
申请号：PCT/US2020/042340
申请日：2020-07-16
申请人： MICRON TECHNOLOGY, INC.
发明人： PRATHER, Matthew, A. , ROONEY, Randall, J.
IPC分类号： G11C11/4096 , G11C7/10 , G06F3/06 , G06F11/3037 , G06F11/3058 , G11C11/4076 , G11C11/4078 , G11C11/4093 , G11C7/1045 , G11C7/1051 , G11C7/1063 , G11C7/1078
摘要： Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

3. 发明申请

WO2023278189A1 MEMORY WRITE METHODS AND CIRCUITS 审中-公开
公开(公告)号：WO2023278189A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/034134
申请日：2022-06-20
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Xiao , CHEN, Po-Hung , HSIEH, Chen-Ju , LI, David , JUNG, Chulmin , PAUL, Ayan
IPC分类号： G11C11/419 , G11C7/10 , G11C7/12 , G11C5/14 , G11C7/1009 , G11C7/1045 , G11C7/1069 , G11C7/1078 , G11C7/1096 , H03K19/018521 , H03K19/1737
摘要： Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

4. 发明申请

WO2021194597A1 COMPUTE NEAR MEMORY WITH BACKEND MEMORY 审中-公开
公开(公告)号：WO2021194597A1
公开(公告)日：2021-09-30
申请号：PCT/US2020/066985
申请日：2020-12-23
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek , SATO, Noriyuki , ATANASOV, Sarah , SUMBUL, Huseyin Ekin , CHEN, Gregory K. , KNAG, Phil , KRISHNAMURTHY, Ram , YOO, Hui Jae , LE, Van H.
IPC分类号： H01L27/108 , H01L27/12 , G11C11/4096 , G11C11/4085 , G11C11/4093 , G11C11/4097 , G11C2211/4066 , G11C5/025 , G11C7/1078 , H01L27/10844 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L27/1266 , H01L28/90
摘要： Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

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