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    • 1. 发明申请
    • RECEIVER TO PROCESS A LOAD MODULATED ANALOG INPUT SIGNAL
    • 接收器处理负载调制的模拟输入信号
    • WO2017084891A1
    • 2017-05-26
    • PCT/EP2016/076635
    • 2016-11-04
    • PANTHRONICS AG
    • JONGSMA, Jakob
    • G06K7/00H04B1/10
    • H04B1/30G06K7/0008
    • A Receiver (17) that receives a load modulated analog input signal (19) and outputs digital data (20) detected in the input signal (19), which receiver (17) comprises: an in-phase mixer (21) that mixes the input signal (19) with an in-phase carrier frequency (22) and provides an in-phase component (23) of the down-converted input signal and a quadrature-phase mixer (24) that mixes the input signal (19) with a quadrature-phase carrier frequency (25) and provides a quadrature-phase component (26) of the down-converted input signal; an amplifier (29, 30) to amplify the in-phase component (23) and the quadrature-phase component (26) of the down-converted input signal; a DC block filter (31) to remove the DC component of the in-phase component (23) and the quadrature-phase component (26), wherein the receiver furthermore comprises: an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in- phase component (23) and the quadrature-phase component (26) to correlate the in-phase component (23) and the quadrature-component (26) with an in-phase component (37) and a quadrature-phase component (38) of a subcarrier or code clock frequency of the input signal (19); a combiner (41) to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer (43) to sample an output signal (42) of the combiner (41) at maximum energy levels to output the digital data (20) detected in the input signal (19).
    • 接收器(17),其接收负载调制的模拟输入信号(19)并输出在输入信号(19)中检测到的数字数据(20),该接收器(17)包括: (21),其将输入信号(19)与同相载波频率(22)混频并提供下变频输入信号的同相分量(23)和正交相位混频器(24),该混频器 将输入信号(19)与正交相位载波频率(25)混合并提供下变频输入信号的正交相位分量(26) 放大器(29,30),用于放大下变频后的输入信号的同相分量(23)和正交分量(26);放大器 一个用于去除同相分量(23)和正交相位分量(26)的直流分量的DC块滤波器(31),其中接收机还包括:同相相关器(33,34)和正交相位器 (23)和正交相位分量(26)中的每一个的相位相关器(35,36),以使同相分量(23)和正交分量(26) 输入信号(19)的副载波或码时钟频率的相位分量(37)和正交相位分量(38)。 组合器(41),用于组合两个同相相关器(33,34)和两个正交相位相关器(35,36)的四个输出信号(48至51); 一个限幅器(43),以最大能级对组合器(41)的输出信号(42)进行采样,以输出在输入信号(19)中检测到的数字数据(20)。
    • 2. 发明申请
    • WASTE CURRENT SENSOR FOR ADAPTIVE WIRELESS CHARGING
    • WO2022167371A1
    • 2022-08-11
    • PCT/EP2022/052230
    • 2022-01-31
    • PANTHRONICS AG
    • SCHLAGER, TobiasPIEBER, MichaelGOITRE, AlessandroANTONETTI, Francesco
    • H02J7/00H02J50/12H02J50/80
    • A system (17) of a power device (1) and a portable device (18) for wireless charging of a battery (3) of the portable device (18), which power device (1) comprises an antenna (4) to receive power adjustment information (16) from the portable device (18) to increase or to decrease the power of the magnetic field emitted by the antenna (4) of the power device (1) and which portable device (18) comprises an antenna (5) exposed to the magnetic field and connected via a matching stage (15) to a rectifier stage (6), to rectify an antenna signal, and which portable device (18) comprises a voltage limiter (19), to limit the rectified antenna signal, and to provide an input voltage (UI) at an input pin (10) of a charger IC (8), which provides a first charge current (IC) at an output pin connected to the battery (3) to charge the battery (3) for a first period of time (T1) as power source with a constant first charge current (IC) wherein the voltage limiter (19) comprises a current sensor (21) positioned in series to the voltage limiter (19) to sense a waste current (IW) deducted from the rectified antenna signal to limit the input voltage (UI) of the charger IC (8) and that the portable device (18) comprises a charge voltage control stage (24), that is built to generate the power adjustment information (16) for the power device (1) to increase or to decrease the power of the magnetic field emitted by the antenna (4) of the power device (1) to steer the waste current (IW) within an upper limit and a lower limit.
    • 3. 发明申请
    • CLOCK SYNCHRONIZER TO SYNCHRONIZE A DEVICE CLOCK WITH A CLOCK OF A REMOTE DEVICE
    • 用同步遥控设备同步装置时钟的时钟同步器
    • WO2017133980A1
    • 2017-08-10
    • PCT/EP2017/051775
    • 2017-01-27
    • PANTHRONICS AG
    • CROLS, JanFELICIJAN, TomazJONGSMA, JakobPIEBER, MichaelNASSAR, Hamzeh
    • H03L7/06H04L27/26
    • H04L27/266H03L7/06H03L7/16
    • A device (1) ) with an antenna that receives a target carrier signal (3) from a remote target (2) and transmits a device carrier signal (6) modulated with data to communicate data between the device (1) and the target (2), which device (1) comprises: clock extraction means (4) to extract a target clock (5) from the target carrier signal (3); driver means (9) to generate the device carrier signal (6) from a device clock (8); synchronization means (7) to synchronize the frequency and phase of the device clock (8) with the target clock (5), wherein that the synchronization means (7) comprise: time measurement means (10) to measure the phase difference between the target clock (5) and the device clock (8) or an internal device clock (33) related to the device clock (8) and to provide a phase information (φ1,φ2,φ3); measurement control means (20) to initiate a first time measurement that results in a first phase information (φ) and to initiate a second time measurement a fixed time period (∆T) after the first time measurement that results in a second phase information (φ2); frequency correction means (11) to correct the frequency of the device clock (8) and/or the internal device clock (33) to the frequency of the target clock (5) based on an evaluation of the first phase information (φ) and second phase information (φ2) by evaluation means (21); which measurement control means (20) are built to initiate a third time measurement after the frequency correction of the device clock (8) and/or the internal device clock (33) that results in a third phase information (φ3) evaluated by the evaluation means (21) and corrected by phase correction means (22) which correct the phase of the device clock (8) to the phase of the target clock (5).
    • 具有天线的设备(1),所述天线从远程目标(2)接收目标载波信号(3)并且发送用数据调制的设备载波信号(6)以在所述天线 设备(1)包括:时钟提取装置(4),用于从目标载波信号(3)中提取目标时钟(5);时钟提取装置 驱动装置(9),用于从设备时钟(8)产生设备载波信号(6); 用于同步装置时钟(8)的频率和相位以及目标时钟(5)的同步装置(7),其中同步装置(7)包括:时间测量装置(10),用于测量目标 时钟(5)和与装置时钟(8)有关的装置时钟(8)或内部装置时钟(33),并提供相位信息(φ1,φ2,φ3)。 测量控制装置(20),用于启动导致第一相位信息(φ)的第一时间测量并且启动第一时间测量之后的固定时间段(ΔT)的第二时间测量,所述第一时间测量导致第二相位信息 φ2); 频率校正装置(11),用于基于对第一相位信息(φ)的评估来将装置时钟(8)和/或内部装置时钟(33)的频率校正为目标时钟(5)的频率; 由评估装置(21)得到第二相位信息(φ2); 所述测量控制装置(20)被建立以在对所述评估评估的第三相位信息(φ3)进行装置时钟(8)和/或内部装置时钟(33)的频率校正之后启动第三时间测量 装置(21),并由相位校正装置(22)校正,该校正装置将装置时钟(8)的相位校正成目标时钟(5)的相位。
    • 6. 发明申请
    • HIGH-VOLTAGE DIGITAL POWER AMPLIFIER WITH SINUSIOIDAL OUTPUT FOR RFID
    • 具有用于RFID的SINUSIOIDAL输出的高电压数字功率放大器
    • WO2017102493A1
    • 2017-06-22
    • PCT/EP2016/080047
    • 2016-12-07
    • PANTHRONICS AG
    • CROLS, JanGABRIELS, StevenJONGSMA, Jakob
    • H03F3/21H03F3/195H03M1/74
    • H03F3/211H03F3/195H03M1/745
    • A Digital power amplifier (13) to drive an RFID antenna (10) with a substantial sinusoidal output current (I) which digital power amplifier (13) comprises: an integrated circuit (IC2) with a first transmission output pin (15) and a second transmission output pin (16) to provide an output signal (17); an adaption circuit (14) of discrete components (C2a, C2b) connected to the first and second transmission output pin (15, 16) to adapt the output signal (17) and feed the substantial sinusoidal output current (I) with a transmission resonance frequency to the RFID antenna (10), wherein the integrated circuit (IC2) comprises: a digital control section (19) with a number of N wave-forming contacts (20) to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; a number of N driver blocks (21) each connected with a first contact (22) to one of the wave-forming contacts (20) and a number of N/2 of them connected with a second contact to the first transmission output pin (15) and the other number of N/2 of them connected with their second contact to the second transmission output pin (16), which driver blocks (21) are built to provide increments of the substantial sinusoidal output current (I) to the first and second transmission output pin (15, 16).
    • 数字功率放大器(13)包括:数字功率放大器(13),用于基本正弦输出电流(I)驱动RFID天线(10);集成电路(IC2),具有第一 传输输出引脚(15)和第二传输输出引脚(16),以提供输出信号(17); - 连接到第一和第二发送输出引脚(15,16)的分立元件(C2a,C2b)的自适应电路(14),以适应输出信号(17)并且馈送基本的正弦输出电流(I) 所述集成电路(IC2)包括:数字控制部分(19),其具有N个波形成触点(20)以输出N位的数字波形位组合和 时钟频率M倍发送谐振频率; 多个N个驱动器块(21),每个驱动器块(21)与第一触点(22)连接到其中一个波形触点(20),并且其中的N / 2个触点块与到第一传输输出引脚的第二触点连接 15),并且其中N / 2个的其中另外N / 2个与它们的第二触点连接到第二变速器输出引脚(16),构建所述驱动器块(21)以向第一 和第二传输输出引脚(15,16)。
    • 7. 发明申请
    • NFC
    • NFC“分体式”架构
    • WO2017067916A1
    • 2017-04-27
    • PCT/EP2016/074955
    • 2016-10-18
    • PANTHRONICS AG
    • PIEBER, MichaelFELICIJAN, TomazJONGSMA, Jakob
    • H04W4/00H04B5/00
    • H04W4/80H04B5/0031H04B5/0056
    • A device (5; 16; 26) that processes a Near Field Communication type application which device (5; 16; 26) comprises: a host controller circuit (3; 27) that processes device applications, that use the Near Field Communication type application, and that processes a host driver (7; 28) that communicates based on a first interface protocol (NCI; EMV); a NFC controller circuit (4; 33) that processes a Near Field Communication type contactless interface (6; 35) and a controller driver (11; 32) that interfaces with the host controller circuit (3; 27), wherein the host controller circuit (3; 27) processes a first transmission module (9; 30) that interfaces with the host driver (7; 28) based on the first interface protocol (NCI; EMV) and with the controller driver (11; 32) based on a second interface protocol, which first transmission module (9; 30) furthermore processes substantially all none-time critical and/or memory consuming tasks of the Near Field Communication type application and wherein the NFC controller circuit (4; 33) comprises a second transmission module (12, 34) that processes all time critical tasks for the Near Field Communication type application towards the Near Field Communication type contactless interface (6; 35).
    • 一种处理近场通信类型应用的设备(5; 16; 26),该设备(5; 16; 26)包括:主控制器电路(3; 27),其处理设备应用, 它们使用近场通信类型应用程序,并且处理基于第一接口协议(NCI; EMV)通信的主机驱动器(7; 28); ,处理与所述主控制器电路(3; 27)接口的近场通信型非接触式接口(6; 35)和控制器驱动器(11; 32)的NFC控制器电路(4; 33),其中所述主控制器电路 (3; 27)基于第一接口协议(NCI; EMV)和控制器驱动器(11; 32)处理与主机驱动器(7; 28)接口的第一传输模块 所述第一传输模块(9; 30)还处理所述近场通信类型应用的基本上所有非时间关键和/或存储器消耗任务,并且其中所述NFC控制器电路(4; 33)包括第二传输模块 (12,34),其处理近场通信类型应用程序朝向近场通信类型非接触式接口(6; 35)的所有时间关键任务。
    • 9. 发明授权
    • NFC “split stack” architecture
    • US10243619B2
    • 2019-03-26
    • US15769652
    • 2016-10-18
    • PANTHRONICS AG
    • Michael PieberTomaz FelicijanJakob Jongsma
    • H04B5/00H04W4/80H04L29/06H04L29/08
    • A device (5; 16; 26) that processes a Near Field Communication type application which device (5; 16; 26) comprises: a host controller circuit (3; 27) that processes device applications, that use the Near Field Communication type application, and that processes a host driver (7; 28) that communicates based on a first interface protocol (NCI; EMV); a NFC controller circuit (4; 33) that processes a Near Field Communication type contactless interface (6; 35) and a controller driver (11; 32) that interfaces with the host controller circuit (3; 27), wherein the host controller circuit (3; 27) processes a first transmission module (9; 30) that interfaces with the host driver (7; 28) based on the first interface protocol (NCI; EMV) and with the controller driver (11; 32) based on a second interface protocol, which first transmission module (9; 30) furthermore processes substantially all none-time critical and/or memory consuming tasks of the Near Field Communication type application and wherein the NFC controller circuit (4; 33) comprises a second transmission module (12, 34) that processes all time critical tasks for the Near Field Communication type application towards the Near Field Communication type contactless interface (6; 35).