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1. 发明授权

US10477249B2 Video processing for masking coding artifacts using dynamic noise maps 有权
公开(公告)号：US10477249B2
公开(公告)日：2019-11-12
申请号：US12479068
申请日：2009-06-05
申请人： Yuxin Liu , Hsi-Jung Wu , Xiaojin Shi , Chris Yoochang Chung
发明人： Yuxin Liu , Hsi-Jung Wu , Xiaojin Shi , Chris Yoochang Chung
IPC分类号： H04N7/12 , H04N11/04 , H04N19/86 , H04N19/46 , H04N19/117 , H04N19/136 , H04N19/44
摘要： A video decoder system includes a video decoding engine, noise database, artifact estimator and post-processing unit. The video coder may generate recovered video from a data stream of coded video data, which may have visually-perceptible artifacts introduced as a byproduct of compression. The noise database may store a plurality of previously developed noise patches. The artifact estimator may estimate the location of coding artifacts present in the recovered video and select noise patches from the database to mask the artifacts and the post-processing unit may integrate the selected noise patches into the recovered video. In this manner, the video decoder may generate post-processed noise which may mask artifacts that otherwise would be generated by a video coding process.

2. 发明授权

US08599238B2 Facial pose improvement with perspective distortion correction 有权
标题翻译：透视失真校正的面部姿态改善
公开(公告)号：US08599238B2
公开(公告)日：2013-12-03
申请号：US12581043
申请日：2009-10-16
申请人： Hsi-Jung Wu , Chris Yoochang Chung , Xiaojin Shi , James Normile
发明人： Hsi-Jung Wu , Chris Yoochang Chung , Xiaojin Shi , James Normile
IPC分类号： H04N7/14
CPC分类号： G06K9/00228 , G06T3/00 , G06T5/006 , G06T2207/20104 , G06T2207/30201 , H04N5/217 , H04N5/23219 , H04N5/23258 , H04N5/23267
摘要： Methods, systems, and apparatus are presented for reducing distortion in an image, such as a video image. A video image can be captured by an image capture device, e.g. during a video conferencing session. Distortion correction processing, such as the application of one or more warping techniques, can be applied to the captured image to produce a distortion corrected image, which can be transmitted to one or more participants. The warping techniques can be performed in accordance with one or more warp parameters specifying a transformation of the captured image. Further, the warp parameters can be generated in accordance with an orientation of the image capture device, which can be determined based on sensor data or can be a fixed value. Additionally or alternatively, the warp parameters can be determined in accordance with a reference image or model to which the captured image should be warped.
摘要翻译：呈现了用于减少诸如视频图像的图像中的失真的方法，系统和装置。视频图像可以由图像捕获设备捕获，例如，在视频会议期间。畸变校正处理，例如应用一个或多个翘曲技术，可以应用于所捕获的图像，以产生可以发送到一个或多个参与者的失真校正图像。翘曲技术可以根据指定捕获图像的变换的一个或多个翘曲参数来执行。此外，可以根据可以基于传感器数据确定的图像捕获装置的取向来生成翘曲参数，或者可以是固定值。附加地或替代地，可以根据捕获的图像应该翘曲的参考图像或模型来确定翘曲参数。

3. 发明申请

US20110090303A1 Facial Pose Improvement with Perspective Distortion Correction 有权
标题翻译：透视畸变修正的面部姿态改善
公开(公告)号：US20110090303A1
公开(公告)日：2011-04-21
申请号：US12581043
申请日：2009-10-16
申请人： Hsi-Jung Wu , Chris Yoochang Chung , Xiaojin Shi , James Normile
发明人： Hsi-Jung Wu , Chris Yoochang Chung , Xiaojin Shi , James Normile
IPC分类号： H04N7/15 , H04N5/217
CPC分类号： G06K9/00228 , G06T3/00 , G06T5/006 , G06T2207/20104 , G06T2207/30201 , H04N5/217 , H04N5/23219 , H04N5/23258 , H04N5/23267
摘要： Methods, systems, and apparatus are presented for reducing distortion in an image, such as a video image. A video image can be captured by an image capture device, e.g. during a video conferencing session. Distortion correction processing, such as the application of one or more warping techniques, can be applied to the captured image to produce a distortion corrected image, which can be transmitted to one or more participants. The warping techniques can be performed in accordance with one or more warp parameters specifying a transformation of the captured image. Further, the warp parameters can be generated in accordance with an orientation of the image capture device, which can be determined based on sensor data or can be a fixed value. Additionally or alternatively, the warp parameters can be determined in accordance with a reference image or model to which the captured image should be warped.
摘要翻译：呈现了用于减少诸如视频图像的图像中的失真的方法，系统和装置。视频图像可以由图像捕获设备捕获，例如，在视频会议期间。畸变校正处理，例如应用一个或多个翘曲技术，可以应用于所捕获的图像，以产生可以发送到一个或多个参与者的失真校正图像。翘曲技术可以根据指定捕获图像的变换的一个或多个翘曲参数来执行。此外，可以根据可以基于传感器数据确定的图像捕获装置的取向来生成翘曲参数，或者可以是固定值。附加地或替代地，可以根据捕获的图像应该翘曲的参考图像或模型来确定翘曲参数。

4. 发明授权

US08731064B2 Post-processing for decoder complexity scalability 有权
标题翻译：后处理解码器复杂度可扩展性
公开(公告)号：US08731064B2
公开(公告)日：2014-05-20
申请号：US11530810
申请日：2006-09-11
申请人： Hsi-Jung Wu , Ionut Hristodorescu , Christian L. Duvivier , James Normile , Jochen Christian Schmidt , Chris Yoochang Chung
发明人： Hsi-Jung Wu , Ionut Hristodorescu , Christian L. Duvivier , James Normile , Jochen Christian Schmidt , Chris Yoochang Chung
IPC分类号： H04N7/12 , H04N7/50 , H04N7/26
CPC分类号： H04N7/26946 , H04N19/117 , H04N19/156 , H04N19/176 , H04N19/196 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/61 , H04N19/70 , H04N19/86
摘要： Systems, apparatuses and methods whereby a base coded video signal is provided to a decoder having a set of post-processing stages. The base coded video signal can be decoded to produce a base decoded video signal. Post-processing of the base decoded video signal can be used to produce an enhanced quality video output signal. Application of a post-processing stage can be implemented according to the capabilities of the decoder and/or the instantaneous operating parameters of the decoder and/or characteristics of a display. A control signal, communicated over a dedicated channel separate from the base coded video signal, can be used initiate and/or aid implementation of a post-processing stage. The control signal can also provide information to assist/manage the decoding of the base coded video signal. The use of additional post-processing stages increases the complexity of an overall decoding process while improving the quality of a resulting reproduced video sequence.
摘要翻译：将基本编码视频信号提供给具有一组后处理级的解码器的系统，装置和方法。基编码视频信号可被解码以产生基本解码视频信号。可以使用基本解码视频信号的后处理来产生增强的质量视频输出信号。后处理阶段的应用可以根据解码器的能力和/或解码器的瞬时操作参数和/或显示器的特性来实现。可以使用通过与基本编码视频信号分开的专用信道传送的控制信号来启动和/或辅助后处理阶段的实现。控制信号还可以提供信息来辅助/管理基本编码视频信号的解码。使用额外的后处理级增加了整体解码过程的复杂性，同时提高了所得到的再现视频序列的质量。

5. 发明授权

US08340194B2 High-yield multi-threading method and apparatus for video encoders/transcoders/decoders with dynamic video reordering and multi-level video coding dependency management 有权
标题翻译：用于具有动态视频重排序和多级视频编码依赖管理的视频编码器/代码转换器/解码器的高产量多线程方法和装置
公开(公告)号：US08340194B2
公开(公告)日：2012-12-25
申请号：US12479336
申请日：2009-06-05
申请人： Jochen Christian Schmidt , Paul Seung Ho Chang , Chris Yoochang Chung , Christian Luc Duvivier , Ionut Hristodorescu , Hsi-Jung Wu , Dazhong Zhang , Xiaosong Zhou
发明人： Jochen Christian Schmidt , Paul Seung Ho Chang , Chris Yoochang Chung , Christian Luc Duvivier , Ionut Hristodorescu , Hsi-Jung Wu , Dazhong Zhang , Xiaosong Zhou
IPC分类号： H04N11/04
CPC分类号： H04N19/436 , H04N19/102 , H04N19/172 , H04N19/174 , H04N19/176 , H04N19/61
摘要： Disclosed is an exemplary video coder and video coding method according to an embodiment of the present invention. The exemplary video coder includes a scheduler, a plurality of processors and a multiplexer. The scheduler can examine processing units in an input buffer to determine an order for the processing unit to be coded by a processor. If the processing unit under examination depends on a processing unit not yet processed, the processing unit under examination can be merged with other processing units, if any, that share a similar dependency. If the processing unit under examination does not depend on any processing units not yet processed, it can be sent to a next available processor for coding. When a processing unit is sent to a processor, any merged processing units that depend on sent processing unit can also be sent to a next available processor.
摘要翻译：公开了根据本发明的实施例的示例性视频编码器和视频编码方法。示例性视频编码器包括调度器，多个处理器和多路复用器。调度器可以检查输入缓冲器中的处理单元以确定处理单元由处理器编码的顺序。如果正在检查的处理单元依赖于尚未处理的处理单元，则被检查的处理单元可以与具有相似依赖性的其他处理单元（如果有的话）合并。如果被检查的处理单元不依赖于尚未处理的任何处理单元，则可将其发送到下一个可用的处理器进行编码。当处理单元被发送到处理器时，依赖于发送的处理单元的任何合并的处理单元也可以被发送到下一个可用的处理器。

6. 发明授权

US07777749B2 Programmable 3D graphics pipeline for multimedia applications 有权
标题翻译：可编程3D图形流水线用于多媒体应用
公开(公告)号：US07777749B2
公开(公告)日：2010-08-17
申请号：US11560630
申请日：2006-11-16
申请人： Chris Yoochang Chung , Donglok Kim , Yongmin Kim
发明人： Chris Yoochang Chung , Donglok Kim , Yongmin Kim
IPC分类号： G06T1/20 , G06T1/00 , G06T11/40 , G06F15/167 , G09G5/00
CPC分类号： G09G5/363 , G06T1/20 , G06T15/005
摘要： A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.
摘要翻译：一种用于处理多个分割的多媒体数据（诸如图形数据，图像数据，视频数据或音频数据）的可编程图形流水线和方法。可编程图形流水线的优选实施例包括执行分区指令的指令高速缓存，寄存器文件和向量功能单元。此外，增强的光栅化单元除了用于图形和其他媒体处理的目的地输出坐标之外还用于生成反映射源坐标。增强的纹理地址单元产生用于图形处理的源纹理数据的相应存储器地址和用于媒体处理的源媒体数据。从存储器检索的数据存储在增强的纹理高速缓存中以供向量功能单元使用。向量输出单元包括用于图形数据的混合单元和用于宽媒体数据的输出缓冲器。

7. 发明授权

US06842177B2 Macroblock padding 有权
标题翻译：宏块填充
公开(公告)号：US06842177B2
公开(公告)日：2005-01-11
申请号：US10020684
申请日：2001-12-14
申请人： Rohit Garg , Chris Yoochang Chung , Coskun Mermer , Donglok Kim , Yongmin Kim
发明人： Rohit Garg , Chris Yoochang Chung , Coskun Mermer , Donglok Kim , Yongmin Kim
IPC分类号： G06T9/00 , G06T11/20
CPC分类号： H04N21/4143 , G06T9/007
摘要： A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.
摘要翻译：视频对象的边界宏块在主机处理器和现有的协处理器之间被填充而没有显着的同步开销。主处理器根据存储在主机存储器中的形状数据确定水平和垂直图形基元。形状数据确定是否应使用点，线或矩形基元来填充宏块中的透明像素。主机处理器将原语传送到协处理器，协处理器以基于交织的流水线方式呈现原语，以便基于存储在视频存储器中的纹理数据来缓冲宏块的透明像素。原语的流程在主处理器到图形协处理器的一个方向上，并且纹理数据不会在主处理器和协处理器之间来回传送。该技术对于使用能够加速MPEG-1/2视频解码的现有协处理器的MPEG-4视频解码的加速特别有用。

8. 发明申请

US20090049287A1 Stall-Free Pipelined Cache for Statically Scheduled and Dispatched Execution 有权
标题翻译：用于静态计划和分派执行的无失调流水线缓存
公开(公告)号：US20090049287A1
公开(公告)日：2009-02-19
申请号：US11839856
申请日：2007-08-16
申请人： Chris Yoochang Chung
发明人： Chris Yoochang Chung
IPC分类号： G06F9/318
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30181 , G06F9/3836 , G06F9/3873
摘要： This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.
摘要翻译：本发明为流水线高速缓存未命中提供灵活的负载延迟。存储器控制器选择插入执行级的一组级联中的一个的输出。该选择可以由加载指令中的延迟字段或先前指令的延迟指定来控制。在绝大多数情况下，本发明是有用的，其中代码可以容忍递减的负载延迟增加以减少高速缓存未命中。

9. 发明授权

US06888892B2 Method for padding macroblocks 有权
标题翻译：填补宏块的方法
公开(公告)号：US06888892B2
公开(公告)日：2005-05-03
申请号：US10015329
申请日：2001-12-10
申请人： Chris Yoochang Chung , Kerem Karadayi , Rohit Garg , Donglok Kim , Yongmin Kim
发明人： Chris Yoochang Chung , Kerem Karadayi , Rohit Garg , Donglok Kim , Yongmin Kim
IPC分类号： G06T11/00 , H04N7/26 , H04N7/12
CPC分类号： G06T9/20 , G06T9/00 , G06T11/001 , H04N19/20
摘要： A method for efficiently padding a macroblock of a video object plane employs two new instructions. The instructions, PadToRight and PadToLeft, are applied in alternating sequence during a PadPass 1 operation and a PadPass 2 operation. The results of these two operations are then averaged to pad each transparent pixel in each row of a macroblock that includes at least one opaque pixel. A Shift_in register is used to temporarily store data to facilitate the operation implemented by these instructions. Once the transparent pixels in each row have been padded horizontally, pixels in rows having shape data equal to zero (indicating all pixels in the row are transparent) are padded in a pre-processing step, followed by an upward propagation step. The two instructions are preferably implemented using 2:1 multiplexers implemented with an arithmetic logic unit. The method is particularly useful in set-top boxes, games, and other video applications.
摘要翻译：一种用于有效地填充视频对象平面的宏块的方法采用两个新的指令。在PadPass 1操作和PadPass 2操作期间，指令PadToRight和PadToLeft以交替顺序应用。然后对这两个操作的结果进行平均以填补包括至少一个不透明像素的宏块的每一行中的每个透明像素。一个Shift_in寄存器用于临时存储数据，以便于这些指令执行的操作。一旦每行中的透明像素已经被水平填充，则具有等于零的形状数据的行中的像素（指示行中的所有像素是透明的）在预处理步骤中被填充，随后是向上传播步骤。两个指令优选地使用由算术逻辑单元实现的2:1复用器来实现。该方法在机顶盒，游戏和其他视频应用中特别有用。

10. 发明授权

US08065505B2 Stall-free pipelined cache for statically scheduled and dispatched execution 有权
标题翻译：无静态流水线缓存，用于静态计划和分派执行
公开(公告)号：US08065505B2
公开(公告)日：2011-11-22
申请号：US11839856
申请日：2007-08-16
申请人： Chris Yoochang Chung
发明人： Chris Yoochang Chung
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30181 , G06F9/3836 , G06F9/3873
摘要： This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.
摘要翻译：本发明为流水线高速缓存未命中提供灵活的负载延迟。存储器控制器选择插入执行级的一组级联中的一个的输出。该选择可以由加载指令中的延迟字段或先前指令的延迟指定来控制。在绝大多数情况下，本发明是有用的，其中代码可以容忍递减的负载延迟增加以减少高速缓存未命中。

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