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1. 发明申请

US20050272213A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US20050272213A1
公开(公告)日：2005-12-08
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

2. 发明授权

US06943085B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
公开(公告)号：US06943085B2
公开(公告)日：2005-09-13
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

3. 发明申请

US20050054173A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US20050054173A1
公开(公告)日：2005-03-10
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/331
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂的源/漏区，然后进行预退火操作。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

4. 发明授权

US07435658B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US07435658B2
公开(公告)日：2008-10-14
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

5. 发明申请

US20050164461A1 Method for forming a junction region of a semiconductor device 有权
标题翻译：用于形成半导体器件的接合区域的方法
公开(公告)号：US20050164461A1
公开(公告)日：2005-07-28
申请号：US10764437
申请日：2004-01-27
申请人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
发明人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/2256 , H01L21/28176 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.
摘要翻译：公开了一种用于形成半导体器件的接合区域的方法。该方法的步骤包括提供半导体衬底。栅极结构形成在半导体衬底上。将掺杂剂注入到半导体衬底中以形成结区域。在栅极结构和半导体衬底上形成绝缘体层。对绝缘体层进行含碳等离子体处理。在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。对半导体基板进行热处理。

6. 发明授权

US06815770B1 MOS transistor having reduced source/drain extension sheet resistance 有权
标题翻译： MOS晶体管具有减少的源极/漏极延伸片电阻
公开(公告)号：US06815770B1
公开(公告)日：2004-11-09
申请号：US10604741
申请日：2003-08-14
申请人： Chin-Cheng Chien , Hsiang-Ying Wang , Yu-Kun Chen , Neng-Hui Yang
发明人： Chin-Cheng Chien , Hsiang-Ying Wang , Yu-Kun Chen , Neng-Hui Yang
IPC分类号： H01L2978
CPC分类号： H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.
摘要翻译：本发明提供了一种新型的MOS晶体管结构。 MOS晶体管包括形成在半导体衬底上的栅电极和形成在栅电极和半导体衬底之间的栅氧化层。在栅电极的每个侧壁上形成间隔物。在间隔物之下形成轻掺杂的源极/漏极延伸部，其中插入在间隔物和半导体衬底之间的凸起的外延层。作为轻掺杂源极/漏极延伸部分的外延层具有大于硅晶体的晶格常数的晶格常数。外延层用作能够增加活性硼浓度，从而降低源极/漏极延伸部的薄层电阻的溶解度增强层。在半导体衬底中，在间隔物的边缘附近形成重掺杂的源/漏区。在重掺杂的源极/漏极区域上形成凸起的硅化物层。

7. 发明授权

US07060547B2 Method for forming a junction region of a semiconductor device 有权
标题翻译：用于形成半导体器件的接合区域的方法
公开(公告)号：US07060547B2
公开(公告)日：2006-06-13
申请号：US10764437
申请日：2004-01-27
申请人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
发明人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/2256 , H01L21/28176 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.
摘要翻译：公开了一种用于形成半导体器件的接合区域的方法。该方法的步骤包括提供半导体衬底。栅极结构形成在半导体衬底上。将掺杂剂注入到半导体衬底中以形成结区域。在栅极结构和半导体衬底上形成绝缘体层。对绝缘体层进行含碳等离子体处理。在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。对半导体基板进行热处理。

8. 发明申请

US20050130434A1 Method of surface pretreatment before selective epitaxial growth 审中-公开
标题翻译：选择性外延生长前的表面预处理方法
公开(公告)号：US20050130434A1
公开(公告)日：2005-06-16
申请号：US10734197
申请日：2003-12-15
申请人： Chin-Cheng Chien , Ya-Lun Cheng , Yu-Ren Wang , Neng-Hui Yang
发明人： Chin-Cheng Chien , Ya-Lun Cheng , Yu-Ren Wang , Neng-Hui Yang
IPC分类号： C30B25/18 , H01L21/20 , H01L21/306 , H01L21/336 , C30B1/00
CPC分类号： H01L21/02046 , C30B25/18 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6659 , H01L29/66636
摘要： A method of surface pretreatment before selective epitaxial growth is provided. A semiconductor substrate having metal-oxide-semiconductor devices formed thereon is provided, and a lightly dry etching process with a carbon-free plasma source is performed to remove a portion of the semiconductor substrate. Then, a selective epitaxial growth process is performed to form a semiconductor layer on the semiconductor substrate. A clean surface for selective epitaxial growth is provided by the lightly dry etching process, which can resolve the undercut issue and surface roughness.
摘要翻译：提供了选择性外延生长前的表面预处理方法。提供其上形成有金属氧化物半导体器件的半导体衬底，并且执行具有无碳等离子体源的轻度干蚀刻工艺以去除半导体衬底的一部分。然后，进行选择性外延生长工艺以在半导体衬底上形成半导体层。用于选择性外延生长的清洁表面通过轻度干蚀刻工艺提供，其可以解决底切问题和表面粗糙度。

9. 发明申请

US20050101093A1 METHOD FOR PREVENTING TO FORM A SPACER UNDERCUT IN SEG PRE-CLEAN PROCESS 有权
标题翻译：防止在SEG预清洗过程中形成间隔器的方法
公开(公告)号：US20050101093A1
公开(公告)日：2005-05-12
申请号：US10705500
申请日：2003-11-12
申请人： Ya-Lun Cheng , Chin-Cheng Chien , Neng-Hui Yang , Yu-Kun Chen
发明人： Ya-Lun Cheng , Chin-Cheng Chien , Neng-Hui Yang , Yu-Kun Chen
IPC分类号： H01L21/302 , H01L21/306 , H01L21/311 , H01L21/336 , H01L21/461 , H01L29/78
CPC分类号： H01L21/02052 , H01L21/31111 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A method for preventing to form a spacer undercut in SEG pre-clean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.
摘要翻译：提供了一种防止在SEG预清洁工艺中形成间隔件底切的方法。本发明利用HFEG溶液同时蚀刻第一间隔物和第二间隔物，同时可防止产生间隔物底切; 去除在半导体衬底的表面上的自然氧化物层。因此，获得半导体衬底上的清洁表面。该方法包括以下步骤：首先，通过DHF（去离子水中的HF）溶液除去半导体衬底表面上的自然氧化物层。然后，通过HFEG（用乙二醇稀释的HF）溶液同时蚀刻第一间隔物和第二间隔物。此外，去除半导体衬底上的自然氧化物。因此，它获得清洁的半导体表面而没有严重的间隔物底切。

10. 发明授权

US06991991B2 Method for preventing to form a spacer undercut in SEG pre-clean process 有权
标题翻译：防止在SEG预清洗过程中形成间隔底切的方法
公开(公告)号：US06991991B2
公开(公告)日：2006-01-31
申请号：US10705500
申请日：2003-11-12
申请人： Ya-Lun Cheng , Chin-Cheng Chien , Neng-Hui Yang , Yu-Kun Chen
发明人： Ya-Lun Cheng , Chin-Cheng Chien , Neng-Hui Yang , Yu-Kun Chen
IPC分类号： H01L21/336 , H01L21/302
CPC分类号： H01L21/02052 , H01L21/31111 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/7834
摘要： A method for preventing to form a spacer undercut in SEG preclean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.
摘要翻译：提供了一种防止在SEG预清洗工艺中形成间隔底切的方法。本发明利用HFEG溶液同时蚀刻第一间隔物和第二间隔物，同时可防止产生间隔物底切; 去除在半导体衬底的表面上的自然氧化物层。因此，获得半导体衬底上的清洁表面。该方法包括以下步骤：首先，通过DHF（去离子水中的HF）溶液除去半导体衬底表面上的自然氧化物层。然后，通过HFEG（用乙二醇稀释的HF）溶液同时蚀刻第一间隔物和第二间隔物。此外，去除半导体衬底上的自然氧化物。因此，它获得清洁的半导体表面而没有严重的间隔物底切。

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