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1. 发明申请

US20080085583A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080085583A1
公开(公告)日：2008-04-10
申请号：US11907162
申请日：2007-10-10
申请人： Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Sun-Jung Kim , Se-Hoon Oh , Young-Sun Kim
发明人： Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Sun-Jung Kim , Se-Hoon Oh , Young-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/02181 , H01L21/0228 , H01L21/02304 , H01L21/3145 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.
摘要翻译：一种制造非易失性存储器件的方法包括在衬底上形成形成隧道隔离层的隧道隔离层，在隧道隔离层上形成导电图案，在导电图案上形成下部氧化硅层，处理表面部分通过氮化处理以在下部氧化硅层上形成第一氧氮化硅层，在第一氮氧化硅层上形成金属氧化物层，在金属氧化物层上形成上部氧化硅层，形成在上氧化硅层上的导电层。

2. 发明授权

US07682906B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07682906B2
公开(公告)日：2010-03-23
申请号：US11907162
申请日：2007-10-10
申请人： Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Sun-Jung Kim , Se-Hoon Oh , Young-Sun Kim
发明人： Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Sun-Jung Kim , Se-Hoon Oh , Young-Sun Kim
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L21/02181 , H01L21/0228 , H01L21/02304 , H01L21/3145 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.
摘要翻译：一种制造非易失性存储器件的方法包括在衬底上形成形成隧道隔离层的隧道隔离层，在隧道隔离层上形成导电图案，在导电图案上形成下部氧化硅层，处理表面部分通过氮化处理以在下部氧化硅层上形成第一氧氮化硅层，在第一氮氧化硅层上形成金属氧化物层，在金属氧化物层上形成上部氧化硅层，形成在上氧化硅层上的导电层。

3. 发明申请

US20080061360A1 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080061360A1
公开(公告)日：2008-03-13
申请号：US11898039
申请日：2007-09-07
申请人： Se-Hoon Oh , Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Sun-Jung Kim
发明人： Se-Hoon Oh , Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Sun-Jung Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。

4. 发明授权

US07635633B2 Non-volatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07635633B2
公开(公告)日：2009-12-22
申请号：US11898039
申请日：2007-09-07
申请人： Se-Hoon Oh , Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Sun-Jung Kim
发明人： Se-Hoon Oh , Young-Geun Park , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Sun-Jung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。

5. 发明授权

US07517750B2 Flash memory devices having multilayered inter-gate dielectric layers including metal oxide layers and methods of manufacturing the same 失效
标题翻译：具有包括金属氧化物层的多层栅极间电介质层的闪存器件及其制造方法
公开(公告)号：US07517750B2
公开(公告)日：2009-04-14
申请号：US11383102
申请日：2006-05-12
申请人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
发明人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.
摘要翻译：本发明的实施例提供了制造存储器件的方法，包括在其上具有有源区的半导体衬底上形成浮置栅极图案，其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层，其中栅极间电介质层通过使用O 3气体作为反应气体在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层，栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极，栅极间电介质层图案和浮置栅极，其中栅极间电介质层图案和控制栅极是顺序堆叠在有源区上，并且在有源区之间形成浮栅，并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

6. 发明授权

US07927950B2 Method of fabricating trap type nonvolatile memory device 有权
标题翻译：陷阱型非易失性存储器件的制造方法
公开(公告)号：US07927950B2
公开(公告)日：2011-04-19
申请号：US11672916
申请日：2007-02-08
申请人： Han-Mei Choi , Chang-Hyun Lee , Seung-Hwan Lee , Young-Geun Park , Sung-Jung Kim , Young-Sun Kim
发明人： Han-Mei Choi , Chang-Hyun Lee , Seung-Hwan Lee , Young-Geun Park , Sung-Jung Kim , Young-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing the cell gate insulating Layer at a temperature of approximately 810° C. to approximately 1370° C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.
摘要翻译：一种制造浮动阱型非易失性存储器件的方法包括：在半导体衬底上形成单元栅极绝缘层，所述栅极绝缘层由下层绝缘层，电荷存储层和上部绝缘层构成; 在大约810℃至大约1370℃的温度下对单元栅极绝缘层进行热退火; 以及在所述热退火单元栅极绝缘层上形成栅电极。

7. 发明申请

US20060072281A1 Methods of forming a layer utilizing a liquid-phase lanthanum precursor and methods of manufacturing a capacitor using the same 审中-公开
标题翻译：使用液相镧前体形成层的方法和使用其制造电容器的方法
公开(公告)号：US20060072281A1
公开(公告)日：2006-04-06
申请号：US11196943
申请日：2005-08-04
申请人： Gab-Jin Nam , Young-Geun Park , Young-Sun Kim , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Cha-Young You
发明人： Gab-Jin Nam , Young-Geun Park , Young-Sun Kim , Han-Mei Choi , Seung-Hwan Lee , Ki-Yeon Park , Cha-Young You
IPC分类号： H01G4/06
CPC分类号： H01L21/02192 , C23C16/40 , H01G4/105 , H01G4/1272 , H01G4/33 , H01L21/02205 , H01L21/02271 , H01L21/0228 , H01L21/3141 , H01L21/31604 , H01L23/5223 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： The present invention can provide methods of forming a layer including lanthanum by utilizing a lanthanum precursor existing in a liquid phase at a room temperature. The present invention can further provide methods of forming layers including lanthanum on objects and methods of manufacturing a capacitor.
摘要翻译：本发明可以提供通过利用在室温下存在于液相中的镧前体形成包含镧的层的方法。本发明还可以提供形成包括镧在内的层的方法和制造电容器的方法。

8. 发明申请

US20070026608A1 FLASH MEMORY DEVICES HAVING MULTILAYERED INTER-GATE DIELECTRIC LAYERS INCLUDING METAL OXIDE LAYERS AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：具有包括金属氧化物层的多层间隙介电层的闪存存储器件及其制造方法
公开(公告)号：US20070026608A1
公开(公告)日：2007-02-01
申请号：US11383102
申请日：2006-05-12
申请人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
发明人： Han-Mei Choi , Young-Geun Park , Seung-Hwan Lee , Young-Sun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Embodiments of the present invention provide methods of manufacturing memory devices including forming floating gate patterns on a semiconductor substrate having active regions thereon, wherein the floating gate patterns cover the active regions and are spaced apart from the active regions; forming an inter-gate dielectric layer on the semiconductor substrate having the floating gate patterns by alternately stacking a zirconium oxide layer and an aluminum oxide layer at least once, wherein the inter-gate dielectric layer is formed by a deposition process using O3 gas as a reactive gas; forming a control gate layer on the inter-gate dielectric layer; and forming a control gate, an inter-gate dielectric layer pattern and a floating gate by sequentially patterning the control gate layer, the inter-gate dielectric layer and the floating gate pattern, wherein the inter-gate dielectric layer pattern and the control gate are sequentially stacked across the active regions, and the floating gate is formed between the active regions and the inter-gate dielectric layer pattern Memory devices, such as flash memory devices are also provided.
摘要翻译：本发明的实施例提供了制造存储器件的方法，包括在其上具有有源区的半导体衬底上形成浮置栅极图案，其中浮置栅极图案覆盖有源区并与有源区间隔开; 通过将氧化锆层和氧化铝层交替层叠至少一次来形成具有浮置栅极图案的半导体衬底上的栅极间电介质层，其中栅极间电介质层通过使用O 2的沉积工艺形成， 3气体作为反应气体; 在所述栅极间电介质层上形成控制栅极层; 以及通过对控制栅极层，栅极间电介质层和浮置栅极图案顺序构图来形成控制栅极，栅极间电介质层图案和浮置栅极，其中栅极间电介质层图案和控制栅极是顺序堆叠在有源区上，并且在有源区之间形成浮栅，并且还提供诸如闪存器件的栅极间电介质层图案存储器件。

9. 发明申请

US20080070368A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080070368A1
公开(公告)日：2008-03-20
申请号：US11902209
申请日：2007-09-20
申请人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yl
发明人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yl
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/792 , H01L21/28185 , H01L21/28194 , H01L21/28282 , H01L21/3185 , H01L29/4234 , H01L29/518 , H01L29/7923
摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.
摘要翻译：在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

10. 发明授权

US08114735B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08114735B2
公开(公告)日：2012-02-14
申请号：US11902209
申请日：2007-09-20
申请人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yi
发明人： Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Han-Mei Choi , Seung-Hwan Lee , Seung-Jae Baik , Sun-Jung Kim , Kwang-Min Park , In-Sun Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28185 , H01L21/28194 , H01L21/28282 , H01L21/3185 , H01L29/4234 , H01L29/518 , H01L29/7923
摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.
摘要翻译：在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

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