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    • 1. 发明授权
    • Semiconductor device and data processor
    • 半导体器件和数据处理器
    • US08018784B2
    • 2011-09-13
    • US12636528
    • 2009-12-11
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/00G11C8/00
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 提高从高速电路块访问低速电路块的速度,而不会显着增加功耗。 Ina数据处理器具有总线控制器,其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,时序控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令,使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器, 响应于针对外围电路的写入指令,使定时控制电路开始与高速时钟信号的周期同步地写入外围电路,并且与该时钟信号同步地终止写入 周期的低速时钟信号。
    • 2. 发明申请
    • SEMICONDUCTOR DEVICE AND DATA PROCESSOR
    • 半导体器件和数据处理器
    • US20100182848A1
    • 2010-07-22
    • US12636528
    • 2009-12-11
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/10H03L7/00H03K17/00
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 提高从高速电路块访问低速电路块的速度,而不会显着增加功耗。 Ina数据处理器具有总线控制器,其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,定时控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令,使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器, 响应于针对外围电路的写入指令,使定时控制电路开始与高速时钟信号的周期同步地写入外围电路,并且与该时钟信号同步地终止写入 周期的低速时钟信号。
    • 3. 发明授权
    • Semiconductor device and data processor
    • 半导体器件和数据处理器
    • US08531893B2
    • 2013-09-10
    • US13674043
    • 2012-11-11
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/10
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 在具有总线控制器的数据处理器中,总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,提供定时控制电路 在外围电路和总线控制器之间,并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号,使定时控制电路响应于指向外围电路的写指令而启动,与高速时钟信号的周期同步地写入外围电路,并且与 低速时钟信号的周期。
    • 4. 发明授权
    • Semiconductor device and data processor
    • 半导体器件和数据处理器
    • US08339869B2
    • 2012-12-25
    • US13220747
    • 2011-08-30
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/00G11C8/00
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 提高从高速电路块访问低速电路块的速度,而不会显着增加功耗。 在具有总线控制器的数据处理器中,总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,提供定时控制电路 在外围电路和总线控制器之间,并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号,使定时控制电路响应于指向外围电路的写指令而启动,与高速时钟信号的周期同步地写入外围电路,并且与 低速时钟信号的周期。
    • 5. 发明授权
    • Laser rewriting apparatus
    • 激光重写装置
    • US08723909B2
    • 2014-05-13
    • US13680943
    • 2012-11-19
    • Toshiaki AsaiYoshihiko HottaShinya KawaharaTomomi Ishimi
    • Toshiaki AsaiYoshihiko HottaShinya KawaharaTomomi Ishimi
    • B41J2/00B41J2/47B41J27/00B41J2/435
    • B41J2/4753B41J2/46B41J2/473
    • A laser rewriting apparatus positioned on one side or the other side of a conveyance path through which a to-be-conveyed object on which a thermoreversible recording medium is affixed is conveyed in a predetermined conveyance direction. The laser rewriting apparatus emits laser light to the thermoreversible recording medium and rewrites an image. The laser writing apparatus includes an image erasing apparatus that emits laser light to the thermoreversible recording medium and erases the image from the thermoreversible recording medium; and an image recording apparatus positioned on the predetermined conveyance direction downstream side of the image erasing apparatus and records a new image by emitting laser light to the thermoreversible recording medium. The image erasing apparatus and the image recording apparatus have the respective laser light emitting parts from which the laser light is emitted at ends on the same side with respect to the predetermined conveyance direction.
    • 位于传送路径的一侧或另一侧上的激光重写装置通过其被固定有热可逆记录介质的待传送物体沿预定传送方向传送。 激光重写装置向热可逆记录介质发射激光并重写图像。 激光写入装置包括:图像擦除装置,其向热可逆记录介质发射激光并从热可逆记录介质擦除图像; 以及位于图像擦除装置的预定输送方向下游侧的图像记录装置,并通过向热可逆记录介质发射激光来记录新图像。 图像擦除装置和图像记录装置具有相对于预定传送方向在相同侧的端部处发射激光的各个激光发射部。
    • 6. 发明授权
    • Method for erasing image on thermoreversible recording medium
    • 在热可逆记录介质上擦除图像的方法
    • US08293679B2
    • 2012-10-23
    • US12561872
    • 2009-09-17
    • Toshiaki AsaiTomomi IshimiShinya KawaharaYoshihiko Hotta
    • Toshiaki AsaiTomomi IshimiShinya KawaharaYoshihiko Hotta
    • B41M5/30G03C1/498
    • B41M5/305B41J2/4753B41M5/3335B41M5/423B41M5/44B41M2205/04B41M2205/38B41M2205/40
    • A method for erasing an image including irradiating an image formed on a thermoreversible recording medium with a laser light having a wavelength of 700 nm to 1,500 nm so as to erase the image, wherein an energy density of the laser light is in a range of the energy density which can erase the image and more than a center value of the range, wherein the thermoreversible recording medium includes a support, and a thermoreversible recording layer on the support, and wherein the thermoreversible recording layer contains a leuco dye serving as an electron-donating color-forming compound and a reversible developer serving as an electron-accepting compound, in which color tone reversibly changes by heat, and at least one of the thermoreversible recording layer and a layer adjacent to the thermoreversible recording layer contains a photothermal conversion material, which absorbs the light and converts the light into heat.
    • 一种擦除图像的方法,包括用波长为700nm至1500nm的激光照射形成在热可逆记录介质上的图像,以便擦除图像,其中激光的能量密度在 能够消除图像的能量密度大于该范围的中心值,其中热可逆记录介质包括载体和支撑体上的热可逆记录层,并且其中热可逆记录层含有用作电子发射层的无色染料, 提供着色形成化合物和作为电子接受性化合物的可逆显影剂,其中色调由热可逆地改变,并且热可逆记录层和与热可逆记录层相邻的层中的至少一个包含光热转换材料, 其吸收光并将光转换成热。
    • 9. 发明申请
    • IMAGE ERASING METHOD AND IMAGE ERASING APPARATUS
    • 图像擦除方法和图像擦除装置
    • US20110090296A1
    • 2011-04-21
    • US12904566
    • 2010-10-14
    • Tomomi ISHIMIShinya KawaharaToshiaki AsaiYoshihiko Hotta
    • Tomomi ISHIMIShinya KawaharaToshiaki AsaiYoshihiko Hotta
    • B41J2/315
    • B41J2/4753B41J2/473B41J29/26B41M5/305B41M5/3335B41M5/3372B41M5/42B41M2205/04B41M2205/36B41M2205/38B41M2205/40
    • An image erasing apparatus including: a semiconductor laser array in which a plurality of semiconductor laser light sources are linearly aligned; a width direction collimating unit provided on an output surface of the semiconductor laser array, and configured to collimate, in a width direction, broadening of laser beams emitted from the semiconductor laser array so as to form a linear beam; and a length direction light distribution controlling unit configured to control a length of a major axis of the linear beam to be longer than a length of a major axis of an emission part of the semiconductor laser array, and to attain uniform light distribution in the length direction of the linear beam; wherein the linear beam, which has the major axis whose length is longer than the length of the major axis of the emission part of the semiconductor laser array and uniform light distribution in the length direction thereof, is to be applied to and heat a thermoreversible recording medium, in which any of transparency and color tone thereof reversibly changes depending on temperature, so as to erase an image recorded on the thermoreversible recording medium.
    • 一种图像擦除装置,包括:半导体激光器阵列,其中多个半导体激光光源线性对准; 宽度方向准直单元,设置在半导体激光器阵列的输出表面上,并且被配置为沿宽度方向准直从半导体激光器阵列发射的激光束的加宽以形成线性光束; 以及长度方向配光控制单元,被配置为将所述线性光束的长轴的长度控制为长于所述半导体激光器阵列的发射部分的长轴的长度,并且在所述长度方向上获得均匀的光分布 线性光束的方向; 其特征在于,将长轴长度比半导体激光器阵列的发射部分的长轴的长度和长度方向均匀的光分布的线性光束施加于热可逆记录 介质,其中任何透明度和其色调根据温度可逆地改变,以便擦除记录在热可逆记录介质上的图像。
    • 10. 发明授权
    • Optical information recording medium, manufacturing method thereof and image processing method
    • 光信息记录介质,其制造方法和图像处理方法
    • US07488701B2
    • 2009-02-10
    • US11091799
    • 2005-03-28
    • Satoshi MizukamiYoshihiko HottaFumiya Ohmi
    • Satoshi MizukamiYoshihiko HottaFumiya Ohmi
    • B41M5/41B32B3/00
    • G11B7/252
    • An object of the present invention is to provide an optical information recording medium by which the getting thereof in and out of a reproducing apparatus and the reproducing of recoding data can be stably and reliably performed and the recording content can be visually confirmed, and which has the reversible display function of performing at least one of the recording, erasing and rewriting of the display which is excellent in the uniformity of the image, easily, with a good appearance and without damaging the optical information recording medium; a manufacturing method of the above-noted optical information recording medium; and an image processing method using the above-noted optical information recording medium. For this object, the present invention provides the optical information recording medium comprising a substrate, an optical information layer disposed on the substrate and a reversible thermosensitive layer in which at least a part of the information recorded in the optical information layer can be recorded in such a manner that the part of the information can be visually recognized, in this order; and further a cushion layer in at least a part of the space between the optical information layer and the reversible thermosensitive layer.
    • 本发明的目的是提供一种光学信息记录介质,通过该光学信息记录介质可以稳定可靠地执行再现设备的进出和重新编码,并且可以目视确认记录内容,并且具有 可以容易地以良好的外观执行图像的均匀性优异的记录,擦除和重写的至少一个的可逆显示功能,并且不损坏光学信息记录介质; 上述光学信息记录介质的制造方法; 以及使用上述光学信息记录介质的图像处理方法。 为此目的,本发明提供了一种光学信息记录介质,其包括基板,设置在基板上的光信息层和可逆热敏层,其中记录在光信息层中的信息的至少一部分可以被记录在其中 信息的一部分可以以这种顺序视觉识别的方式; 以及在光学信息层和可逆热敏层之间的空间的至少一部分中的缓冲层。