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1. 发明授权

US08043770B2 Photomask and method of forming overlay vernier of semiconductor device using the same 失效
标题翻译：光掩模和使用其形成半导体器件的覆盖游标的方法
公开(公告)号：US08043770B2
公开(公告)日：2011-10-25
申请号：US12133565
申请日：2008-06-05
申请人： Yong Hyun Lim
发明人： Yong Hyun Lim
IPC分类号： G03F1/00
CPC分类号： G03F9/708 , G03F1/48 , G03F9/7076 , G03F9/7084
摘要： This patent relates to a photomask and a method of forming an overlay vernier of a semiconductor device employing the same. The photomask includes a reticle formed of a first material through which light can transmit, a first pattern formed on the reticle and formed of a material through which light cannot transmit, a second pattern having a size smaller than the first pattern, and an auxiliary pattern formed to come in contact with the first pattern and formed of a second material different from the first material of the reticle. Thus, inclination is formed on side portions of the overlay vernier and a thin film may be easily formed on the overlay vernier.
摘要翻译：该专利涉及一种光掩模和使用其的半导体器件的覆盖游标的形成方法。光掩模包括由光可透射的第一材料形成的掩模版，形成在掩模版上并由光不能透射的材料形成的第一图案，具有小于第一图案的尺寸的第二图案，以及辅助图案形成为与第一图案接触并由与掩模版的第一材料不同的第二材料形成。因此，在覆盖游标的侧部形成倾斜，并且可以容易地在覆盖游标上形成薄膜。

2. 发明授权

US09431336B2 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09431336B2
公开(公告)日：2016-08-30
申请号：US13598569
申请日：2012-08-29
申请人： Yong Hyun Lim
发明人： Yong Hyun Lim
IPC分类号： H01L27/115 , H01L23/50
CPC分类号： H01L21/76816 , H01L21/76805 , H01L21/76808 , H01L21/7681 , H01L21/76877 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.
摘要翻译：半导体器件包括：衬底，包括存储单元区域和接触区域;串联结构，包括导电层和第一层间绝缘层，交替地层叠在衬底上并从存储单元区域朝向接触区域向下层突出;阻挡肋图案在接触区域中的导电层上彼此间隔开并且被配置为通过间隔空间打开接触区域中的导电层的层，以及填充到相邻的隔壁图案之间的空间中的第一接触插塞和耦合到接触区域中的导电层。

3. 发明申请

US20090325360A1 Method of Forming Trench of Semiconductor Device 审中-公开
标题翻译：形成半导体器件沟槽的方法
公开(公告)号：US20090325360A1
公开(公告)日：2009-12-31
申请号：US12492806
申请日：2009-06-26
申请人： Yong Hyun Lim
发明人： Yong Hyun Lim
IPC分类号： H01L21/28 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/308
摘要： The invention relates to a method of forming a trench of a semiconductor device. According to the method, a semiconductor substrate including a first region and a second region is provided. A gate insulating layer, a gate conductive layer, and a hard mask pattern are formed over the semiconductor substrate. First trenches are simultaneously formed in respective isolation areas of the first region and the second region by etching the gate conductive layer, the gate insulating layer, and the semiconductor substrate using an etch process employing the hard mask pattern. A second trench having a recess is formed on a bottom of the first trench formed in the second region. The recess is formed by widening the first trench by further etching the first trench.
摘要翻译：本发明涉及形成半导体器件沟槽的方法。根据该方法，提供包括第一区域和第二区域的半导体衬底。在半导体衬底上形成栅极绝缘层，栅极导电层和硬掩模图案。通过使用采用硬掩模图案的蚀刻工艺，通过蚀刻栅极导电层，栅极绝缘层和半导体衬底，在第一区域和第二区域的相应隔离区域中同时形成第一沟槽。具有凹部的第二沟槽形成在形成在第二区域中的第一沟槽的底部上。通过进一步蚀刻第一沟槽来扩大第一沟槽形成凹部。

4. 发明申请

US20090023079A1 Photomask and Method of Forming Overlay Vernier of Semiconductor Device Using the Same 失效
标题翻译：光掩模和使用其形成半导体器件的叠加游标的方法
公开(公告)号：US20090023079A1
公开(公告)日：2009-01-22
申请号：US12133565
申请日：2008-06-05
申请人： Yong Hyun Lim
发明人： Yong Hyun Lim
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F9/708 , G03F1/48 , G03F9/7076 , G03F9/7084
摘要： This patent relates to a photomask and a method of forming an overlay vernier of a semiconductor device employing the same. The photomask includes a reticle formed of a first material through which light can transmit, a first pattern formed on the reticle and formed of a material through which light cannot transmit, a second pattern having a size smaller than the first pattern, and an auxiliary pattern formed to come in contact with the first pattern and formed of a second material different from the first material of the reticle. Thus, inclination is formed on side portions of the overlay vernier and a thin film may be easily formed on the overlay vernier.
摘要翻译：该专利涉及一种光掩模和使用其的半导体器件的覆盖游标的形成方法。光掩模包括由光可透射的第一材料形成的掩模版，形成在掩模版上并由光不能透射的材料形成的第一图案，具有小于第一图案的尺寸的第二图案，以及辅助图案形成为与第一图案接触并由与掩模版的第一材料不同的第二材料形成。因此，在覆盖游标的侧部形成倾斜，并且可以容易地在覆盖游标上形成薄膜。

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