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1. 发明授权

US07078945B2 Semiconductor device having logic circuit and macro circuit 失效
标题翻译：具有逻辑电路和宏电路的半导体器件
公开(公告)号：US07078945B2
公开(公告)日：2006-07-18
申请号：US11045104
申请日：2005-01-31
申请人： Yasushige Ogawa , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Yoshiyuki Ishida
IPC分类号： H03L7/00
CPC分类号： G11C29/12005 , G11C7/1006 , G11C7/22 , G11C29/02 , G11C2029/0401 , G11C2029/5006 , G11C2207/2227
摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.
摘要翻译：半导体器件包括逻辑电路和宏电路。宏电路包括消耗直流（DC）电路。为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

2. 发明授权

US07167042B2 Semiconductor device having logic circuit and macro circuit 有权
标题翻译：具有逻辑电路和宏电路的半导体器件
公开(公告)号：US07167042B2
公开(公告)日：2007-01-23
申请号：US10757395
申请日：2004-01-15
申请人： Yasushige Ogawa , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Yoshiyuki Ishida
IPC分类号： G05F3/02
CPC分类号： G11C29/12005 , G11C7/1006 , G11C7/22 , G11C29/02 , G11C2029/0401 , G11C2029/5006 , G11C2207/2227
摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.
摘要翻译：半导体器件包括逻辑电路和宏电路。宏电路包括消耗直流（DC）电路。为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

3. 发明授权

US06943616B2 Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件及半导体集成电路器件的调整方法
公开(公告)号：US06943616B2
公开(公告)日：2005-09-13
申请号：US10648272
申请日：2003-08-27
申请人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
发明人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
IPC分类号： H01L27/04 , G01R31/3167 , H01L21/822 , H03M1/10 , H03M1/66 , G05F1/10
CPC分类号： H03M1/1019 , G01R31/3167 , H03M1/66
摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.
摘要翻译：本发明旨在提供一种半导体集成电路装置的半导体集成电路装置和调整方法，能够调整从内置的模拟信号生成部输出的模拟信号而不将其输出为模拟值。从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。判断信号JG作为内部信号作用在预定信号存储部分4上，并且将调整信号AD提取到预定信号存储部分4中。此外，判断信号JG通过外部端子T 2作为数字信号输出，外部测试装置获取调整信号，并将取得的调整信号存储在规定的信号存储部4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置并且根据简单的测试方法准确而快速地执行调整测试。

4. 发明申请

US20050127985A1 Semiconductor device having logic circuit and macro circuit 失效
标题翻译：具有逻辑电路和宏电路的半导体器件
公开(公告)号：US20050127985A1
公开(公告)日：2005-06-16
申请号：US11045104
申请日：2005-01-31
申请人： Yasushige Ogawa , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Yoshiyuki Ishida
IPC分类号： G06F1/32 , G11C5/14 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/408 , G11C11/413 , G11C29/02 , H01L21/822 , H01L27/04 , H01L27/10 , H03L7/00
CPC分类号： G11C29/12005 , G11C7/1006 , G11C7/22 , G11C29/02 , G11C2029/0401 , G11C2029/5006 , G11C2207/2227
摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.
摘要翻译：半导体器件包括逻辑电路和宏电路。宏电路包括消耗直流（DC）电路。为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

5. 发明授权

US06307801B1 Trimming circuit for system integrated circuit 有权
标题翻译：系统集成电路微调电路
公开(公告)号：US06307801B1
公开(公告)日：2001-10-23
申请号：US09443886
申请日：1999-11-19
申请人： Yasushige Ogawa , Eisaku Itoh , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Eisaku Itoh , Yoshiyuki Ishida
IPC分类号： G11C800
CPC分类号： G11C5/143 , G11C5/147
摘要： A system LSI circuit which includes multiple memory circuits and functional logic circuits includes a control circuit for controlling the voltage supplied to the memory circuits. The control circuit includes trimming circuits for adjusting the memory supply voltages to ensure that the supplied voltages are within predetermined tolerances. The control circuit services all of the memory circuits, such that redundant logic functions are consolidated and multiple pads are not required to measure the memory supply voltages.
摘要翻译：包括多个存储器电路和功能逻辑电路的系统LSI电路包括用于控制提供给存储电路的电压的控制电路。控制电路包括用于调节存储器电源电压的修整电路，以确保所提供的电压在预定的公差范围内。控制电路为所有存储器电路提供服务，使得冗余逻辑功能被整合，并且不需要多个焊盘来测量存储器电源电压。

6. 发明申请

US20050270871A1 Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件及半导体集成电路器件的调整方法
公开(公告)号：US20050270871A1
公开(公告)日：2005-12-08
申请号：US11198225
申请日：2005-08-08
申请人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
发明人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
IPC分类号： H01L27/04 , G01R31/3167 , H01L21/822 , H03M1/10 , H03M1/66 , G11C7/00
CPC分类号： H03M1/1019 , G01R31/3167 , H03M1/66
摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.
摘要翻译：本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。判断信号JG作为内部信号作用于预定信号存储部分4，并且调节信号AD被取出到预定信号存储部分4.此外，判断信号JG通过外部端子T 2作为数字信号输出，外部测试器装置获取调整信号并将获取的调节信号存储在预定信号存储部分4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置进行调整测试，根据简单的测试方法准确快速。

7. 发明授权

US06700437B1 Semiconductor device including logic circuit and macro circuit which has a function for stopping a direct current 有权
标题翻译：包括逻辑电路和诸如存储电路的宏电路的半导体器件，其具有用于停止直流电的功能
公开(公告)号：US06700437B1
公开(公告)日：2004-03-02
申请号：US09642937
申请日：2000-08-22
申请人： Yasushige Ogawa , Yoshiyuki Ishida
发明人： Yasushige Ogawa , Yoshiyuki Ishida
IPC分类号： G05F110
CPC分类号： G11C29/12005 , G11C7/1006 , G11C7/22 , G11C29/02 , G11C2029/0401 , G11C2029/5006 , G11C2207/2227
摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.
摘要翻译：半导体器件包括逻辑电路和宏电路。宏电路包括消耗直流（DC）电路。为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

8. 发明授权

US06269033B1 Semiconductor memory device having redundancy unit for data line compensation 有权
标题翻译：半导体存储器件具有用于数据线补偿的冗余单元
公开(公告)号：US06269033B1
公开(公告)日：2001-07-31
申请号：US09480619
申请日：2000-01-10
申请人： Yoshiyuki Ishida , Yasushige Ogawa
发明人： Yoshiyuki Ishida , Yasushige Ogawa
IPC分类号： G11C702
CPC分类号： G11C29/848
摘要： A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.
摘要翻译：诸如SDRAM的半导体存储器件包括输入/输出数据线对，数据总线线对和冗余数据总线对。输入/输出数据线对通过冗余移位开关连接到数据总线线对中的相应一条数据总线线对，其中最后一条输入/输出数据线对连接到最后一个数据总线线对和冗余数据总线对。读数缓冲器和写放大器连接在每个数据总线线对和冗余数据线对之间。移位开关位于比读出缓冲器和写入放大器更靠近输入/输出数据线对的位置，使得从存储器单元读取的数据不受开关的导通电阻和寄生电容的影响。当开关位于比读取缓冲器和写入放大器更靠近数据总线时，开关影响从存储器单元读取的数据的数据信号。

9. 发明授权

US07459960B2 Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的调整方法
公开(公告)号：US07459960B2
公开(公告)日：2008-12-02
申请号：US11444401
申请日：2006-06-01
申请人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
发明人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
IPC分类号： G05F1/10
CPC分类号： H03M1/1019 , G01R31/3167 , H03M1/66
摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.
摘要翻译：本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。判断信号JG作为内部信号作用在预定信号存储部分4上，并且调节信号AD被取出到预定信号存储部分4.此外，判断信号JG通过外部端子T2和外部信号作为数字信号输出测试器装置获取调整信号并将获取的调节信号存储在预定信号存储部分4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置进行调整测试，并根据准确快速地进行简单的测试方法。

10. 发明申请

US20060214724A1 Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件及半导体集成电路器件的调整方法
公开(公告)号：US20060214724A1
公开(公告)日：2006-09-28
申请号：US11444401
申请日：2006-06-01
申请人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
发明人： Yasushige Ogawa , Yoshiyuki Ishida , Masato Matsumiya
IPC分类号： G05F1/10
CPC分类号： H03M1/1019 , G01R31/3167 , H03M1/66
摘要： It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.
摘要翻译：本发明旨在提供一种半导体集成电路器件的半导体集成电路器件和调整方法，该半导体集成电路器件能够调整从内置的模拟信号产生部分输出的模拟信号而不将其输出为模拟值。从输入调整信号AD的模拟信号生成部3输出模拟信号AOUT。模拟信号AOUT被输入到判断部分1，在判定部分1中，以预定值进行比较和判断，然后输出判断信号JG。判断信号JG作为内部信号作用在预定信号存储部分4上，并且将调整信号AD提取到预定信号存储部分4中。此外，判断信号JG通过外部端子T 2作为数字信号输出，外部测试装置获取调整信号，并将取得的调整信号存储在规定的信号存储部4中。因此，可以将模拟信号调整为模拟值而不输出到外部，并且可以使用简单的测试装置并且根据简单的测试方法准确而快速地进行调整测试。

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