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1. 发明授权

US5729153A Output buffer with oscillation damping 失效
标题翻译：具有振荡阻尼的输出缓冲器
公开(公告)号：US5729153A
公开(公告)日：1998-03-17
申请号：US559864
申请日：1995-11-20
申请人： Yachin Afek , Vladimir Koifman , Natan Baron , Eytan Engel
发明人： Yachin Afek , Vladimir Koifman , Natan Baron , Eytan Engel
IPC分类号： H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361
摘要： Oscillation of the output (16, 17) of an integrated circuit output buffer (43) is automatically damped by sensing ground lead (18) transients as the buffer output (16, 17) changes, and when the ground lead (18) swing is large enough, using the sensed change to apply a turn-off signal of the appropriate polarity to a transistor (N1) serially placed in the output buffer (43) to add resistance during the transition. The added resistance damps out the oscillations quickly to prevent rebound of the buffer output voltage past the logic transition threshold (Vol). An RC time constant (R1, C1) controls the duration of the added resistance which disappears after the transition is complete. The action of a damping control circuit (45) is speed dependent so that greater damping is provided for fast transitions when oscillations would be more sever and no damping during slow transitions when damping is not needed.
摘要翻译：集成电路输出缓冲器（43）的输出（16,17）的振荡由于缓冲器输出（16,17）变化而通过感测接地引线（18）瞬变而被自动衰减，并且当接地引线（18）摆动为足够大，使用感测到的改变将适当极性的关断信号施加到串联放置在输出缓冲器（43）中的晶体管（N1），以在转换期间增加电阻。增加的电阻快速阻止振荡，以防止缓冲器输出电压的反弹超过逻辑转换阈值（Vol）。 RC时间常数（R1，C1）控制转换完成后消失的增加电阻的持续时间。阻尼控制电路（45）的作用是速度依赖性的，因此当不需要阻尼时，振荡将更加严密，并且在缓慢转变期间没有阻尼，因此为快速过渡提供更大的阻尼。

2. 发明授权

US5966029A Multi-bit exclusive or 失效
标题翻译：多位独占或
公开(公告)号：US5966029A
公开(公告)日：1999-10-12
申请号：US893043
申请日：1997-07-15
申请人： Moshe Tarrab , Eytan Engel , Natan Baron , Dan Kuzmin
发明人： Moshe Tarrab , Eytan Engel , Natan Baron , Dan Kuzmin
IPC分类号： H03K19/21
CPC分类号： H03K19/21
摘要： The present invention relates to multi-bit exclusive-or (XOR) gates (60), including those where N parallel input bits (36, 38) are XORed with one data input bit (52). A modular approach is made using only one basic cell (30) for various implementations with different propagation delays. An N-bit XOR comprises basic cells (30) of adjacent first and second XOR gates (32, 34). Each first XOR gate (32) processes as input two of said N primary input bits (36, 38) and each second XOR gate (34) processes as input bits output bits of first or second XOR gates (32, 34) or the input data bit (52). This structure makes it possible to create an array of identical basic cells which is very suitable for VLSI implementation. There are few lines of connections between the different cells in the cell array which leads to substantial reduction in propagation delay without adding substantial wiring or layout complexity.
摘要翻译：本发明涉及多位异或（XOR）门（60），包括其中N个并行输入位（36,38）与一个数据输入位（52）进行异或运算的门。仅使用一个基本单元（30）进行模块化处理，用于具有不同传播延迟的各种实现。 N位XOR包括相邻的第一和第二异或门（32,34）的基本单元（30）。每个第一XOR门（32）作为所述N个主要输入位（36,38）中的两个进行处理，并且每个第二异或门（34）作为第一或第二异或门（32,34）的输入位或输入数据位（52）。该结构使得可以创建非常适合VLSI实现的相同基本单元阵列。在单元阵列中的不同单元之间存在很少的连接线，导致传播延迟的显着降低，而不增加实质的布线或布局的复杂性。

3. 发明授权

US5751178A Apparatus and method for shifting signal levels 失效
标题翻译：用于移位信号电平的装置和方法
公开(公告)号：US5751178A
公开(公告)日：1998-05-12
申请号：US767094
申请日：1996-12-05
申请人： Joseph Shor , Eytan Engel , Natan Baron
发明人： Joseph Shor , Eytan Engel , Natan Baron
IPC分类号： H03K17/10 , H03K19/0185 , H03K5/153
CPC分类号： H03K17/102 , H03K19/018521
摘要： The electronic circuit (100) of the invention receives first signals DATA (170) having logical "1" at high (VCCH) or low (VCCL) levels and logical "0" at reference level (ZERO) and generates second signals OUT (186) between high level (VCCH) and reference level (ZERO) without changing the information. The circuit comprises a first switch (161) and a second switch (161) serially coupled together to a common output node (103). The first switch (162) is controlled by a control signal (CTRL) derived from DATA, OUT, or optionally from a clock signal CLK. The first switch (161) is switched off before the second switch (162) is switched off. Contention (conducting at the same time) is thereby avoided and the first switch (161) and the second switch (162) can be implemented by substantially equal-sized components.
摘要翻译：本发明的电子电路（100）在高（VCCH）或低（VCCL）电平处接收具有逻辑“1”的第一信号DATA（170），并在基准电平（ZERO）处接收逻辑“0”，并产生第二信号OUT（186 ）在高电平（VCCH）和参考电平（ZERO）之间，而不改变信息。电路包括串联耦合到公共输出节点（103）的第一开关（161）和第二开关（161）。第一开关（162）由从DATA，OUT或可选地从时钟信号CLK导出的控制信号（CTRL）来控制。在第二开关（162）关闭之前，第一开关（161）被断开。因此避免了同时进行的竞争（第一开关161和第二开关162）可以通过基本相等的部件来实现。

4. 发明授权

US07936388B2 Apparatus and a method for low noise sensing 有权
标题翻译：低噪声感测装置及方法
公开(公告)号：US07936388B2
公开(公告)日：2011-05-03
申请号：US10566783
申请日：2004-11-17
申请人： Vladimir Koifman , Natan Baron
发明人： Vladimir Koifman , Natan Baron
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/363
摘要： The invention provides a method and apparatus. The apparatus includes a pixels (10) adapted to receive light and to output a current representative of the received light; a feedback circuitry (20), connected to the pixel (10), adapted to receive said current and to receive a reference current (Iref) and to provide a feedback signal to the pixel (10) at least during at least a reset stage of the pixel (10). The method includes: (i) receiving light, by a pixel 10), and providing a pixel output signal representative of the received light; (ii) receiving, by a feedback circuitry, the pixel output signal; and (iii) providing multiple feedback signals to the pixel at least during a reset stage of the pixel (10).
摘要翻译：本发明提供了一种方法和装置。该装置包括适于接收光并输出表示所接收的光的电流的像素（10）; 连接到所述像素（10）的反馈电路（20），适于接收所述电流并接收参考电流（Iref），并且至少在至少在复位阶段期间向所述像素（10）提供反馈信号像素（10）。该方法包括：（i）通过像素10）接收光，并提供表示所接收的光的像素输出信号; （ii）通过反馈电路接收像素输出信号; 以及（iii）至少在所述像素（10）的复位阶段期间向所述像素提供多个反馈信号。

5. 发明申请

US20070188639A1 Apparatus and a method for low noise sensing 有权
标题翻译：低噪声感测装置及方法
公开(公告)号：US20070188639A1
公开(公告)日：2007-08-16
申请号：US10566783
申请日：2003-12-11
申请人： Vladimir Koifman , Natan Baron
发明人： Vladimir Koifman , Natan Baron
IPC分类号： H04N5/335
CPC分类号： H04N5/363
摘要： The invention provides a method and apparatus. The apparatus includes a pixel (10) adapted to receive light and to output a current representative of the received light; a feedback circuitry (20), connected to the pixel (10), adapted to receive said current and to receive a reference current (Iref) and to provide a feedback signal to the pixel (10) at least during at least a reset stage of the pixel (10). The method includes: (i) receiving light, by a pixel 10), and providing a pixel output signal representative of the received light; (ii) receiving, by a feedback circuitry, the pixel output signal; and (iii) providing multiple feedback signals to the pixel at least during a reset stage of the pixel (10).
摘要翻译：本发明提供了一种方法和装置。该装置包括适于接收光并输出表示所接收的光的电流的像素（10）; 连接到所述像素（10）的反馈电路（20），适于接收所述电流并接收参考电流（Iref），并且至少在至少在复位阶段期间向所述像素（10）提供反馈信号像素（10）。该方法包括：（i）通过像素10）接收光，并提供表示所接收的光的像素输出信号; （ii）通过反馈电路接收像素输出信号; 以及（iii）至少在所述像素（10）的复位阶段期间向所述像素提供多个反馈信号。

6. 发明授权

US5845098A Address lines load reduction 失效
标题翻译：地址线减少负载
公开(公告)号：US5845098A
公开(公告)日：1998-12-01
申请号：US669680
申请日：1996-06-24
申请人： David Galanti , Eitan Zmora , Natan Baron , Kevin Kloker
发明人： David Galanti , Eitan Zmora , Natan Baron , Kevin Kloker
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4213
摘要： Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.
摘要翻译：子系统（12-20）由包括较高地址线（62,64）和低位地址线（60）的总线（44）耦合。一个或多个子系统（20）具有地址连接（202），用于接收标识该子系统（20）内的地址空间（INT）的低阶地址（76'）。该连接（202）耦合到总线（44）的较高地址线（62,64）。地址发生器（22）提供子系统选择（CS）地址和低阶（INT）地址。耦合在地址发生器（22）和总线（44）之间的控制装置（24）使用子系统选择（CS）地址将来自地址发生器（22）的低阶（INT）地址动态地耦合到较高阶当子系统选择（CS）地址用于所选择的子系统（20）时，总线（62,64）。这减少了耦合到较低级总线（60）的子系统（12-20）的数量，并且有助于使总线（44）负载均衡。

7. 发明授权

US4831343A Crystal clock generator having fifty percent duty cycle 失效
标题翻译：水晶钟发生器占空比为百分之五十
公开(公告)号：US4831343A
公开(公告)日：1989-05-16
申请号：US172517
申请日：1988-03-24
申请人： Natan Baron
发明人： Natan Baron
IPC分类号： H03K3/017 , H03K3/03 , H03K5/08
CPC分类号： H03K3/0307 , H03K3/017 , H03K5/08
摘要： A crystal oscillator circuit having an accurate duty cycle at very high frequency is provided. An oscillator stage is provided which receives regenerative feedback from an inverter to sustain oscillation. The oscillator stage provides an AC output signal having a first average DC value determined by the regenerative feedback. The AC signal is coupled to a clipping circuit which symmetrically clips the AC signal about a predetermined second average DC level at first and second predetermined voltage levels. The inverter receives the clipped signal and provides an oscillating clock signal with an accurate duty cycle in response thereto.
摘要翻译：提供了具有非常高频率的精确占空比的晶体振荡器电路。提供振荡器级，其接收来自逆变器的再生反馈以维持振荡。振荡器级提供具有由再生反馈确定的第一平均DC值的AC输出信号。 AC信号耦合到限幅电路，该钳位电路在第一和第二预定电压电平下以预定的第二平均DC电平对称地夹紧AC信号。逆变器接收限幅信号并响应于此提供具有精确占空比的振荡时钟信号。

8. 发明申请

US20070189604A1 Method and apparatus for camera shake compensation 有权
标题翻译：摄像机抖动补偿的方法和装置
公开(公告)号：US20070189604A1
公开(公告)日：2007-08-16
申请号：US10566920
申请日：2004-11-17
申请人： Natan Baron , Valadimir Koifman
发明人： Natan Baron , Valadimir Koifman
IPC分类号： G06K9/00
CPC分类号： H04N5/23267 , H04N5/23248 , H04N5/23254 , H04N5/349
摘要： The invention provides a method for providing an image, the method includes: exposing a first group of pixels located at a first location to light, during an intermediate exposure period, to provide analog signals representative of the light; and transferring the analog signals to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift; then further exposure of the second group of pixels etc. The invention provides an apparatus for camera shake compensation, the apparatus includes: (i) a two dimensional array pixels, whereas multiple pixels of the array are adapted to receive light during an intermediate exposure period, and in response to provide analog signals representative of the light; and are further adapted to alter their condition in response to a reception of a right-back signals representative of previously received light; (ii) an analog memory, adapted to receive and store analog signals representative of light received a first group of pixels within the pixel array; and (iii) a write back circuitry, adapted to write back stored analog signals received from the first group to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift.
摘要翻译：本发明提供了一种用于提供图像的方法，所述方法包括：在中间曝光期间，将位于第一位置处的第一组像素曝光以提供表示光的模拟信号; 以及将模拟信号传送到位于第二位置的第二组像素; 而第一和第二位置之间的关系响应于估计的图像间移位; 然后进一步曝光第二组像素等。本发明提供了一种用于相机抖动补偿的装置，该装置包括：（i）二维阵列像素，而阵列的多个像素适于在中间曝光周期期间接收光并且响应于提供代表光的模拟信号; 并且还适于响应于代表先前接收到的光的右后卫的接收来改变其状况; （ii）模拟存储器，适于接收和存储代表光的模拟信号，所述模拟信号接收所述像素阵列内的第一组像素; 和（iii）写回电路，用于将存储的从第一组接收的模拟信号写回位于第二位置的第二组像素; 而第一和第二位置之间的关系响应于估计的图像间偏移。

9. 发明授权

US5742621A Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor 失效
标题翻译：用于在数据处理系统中实现加法比较选择蝶形运算的方法及其指令
公开(公告)号：US5742621A
公开(公告)日：1998-04-21
申请号：US554329
申请日：1995-11-02
申请人： Yossi Amon , Natan Baron
发明人： Yossi Amon , Natan Baron
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H04L25/08
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/30101 , G06F9/30112 , H03M13/4107 , H03M13/4184 , H03M13/6569
摘要： A parallel data structure and a dedicated Viterbi shift left instruction minimize the number of clock cycles required for decoding a convolutionally encoded signal in a data processing system (20) in software. Specifically, the data structure and Viterbi shift left instruction reduce the number of clock cycles required for performing an add-compare-select butterfly operation. The add-compare-select butterfly operation is included in a DO loop in a plurality of instructions for executing a Viterbi decoding algorithm, and is repeated a predetermined number of times, for choosing the best path through a trellis diagram.
摘要翻译：并行数据结构和专用维特比移位左指令以软件最小化在数据处理系统（20）中解码卷积编码信号所需的时钟周期数。具体地说，数据结构和维特比左移指令减少执行加法比较选择蝶形运算所需的时钟周期数。加法比较选择蝶形运算被包括在用于执行维特比解码算法的多个指令中的DO循环中，并且重复预定次数，用于选择通过网格图的最佳路径。

10. 发明授权

US08013900B2 Method and apparatus for camera shake compensation 有权
标题翻译：摄像机抖动补偿的方法和装置
公开(公告)号：US08013900B2
公开(公告)日：2011-09-06
申请号：US10566920
申请日：2004-11-17
申请人： Natan Baron , Valadimir Koifman
发明人： Natan Baron , Valadimir Koifman
IPC分类号： H04N5/228
CPC分类号： H04N5/23267 , H04N5/23248 , H04N5/23254 , H04N5/349
摘要： The invention provides a method for providing an image, the method includes: exposing a first group of pixels located at a first location to light, during an intermediate exposure period, to provide analog signals representative of the light; and transferring the analog signals to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift; then further exposure of the second group of pixels etc. The invention provides an apparatus for camera shake compensation, the apparatus includes: (i) a two dimensional array pixels, whereas multiple pixels of the array are adapted to receive light during an intermediate exposure period, and in response to provide analog signals representative of the light; and are further adapted to alter their condition in response to a reception of a right-back signals representative of previously received light; (ii) an analog memory, adapted to receive and store analog signals representative of light received a first group of pixels within the pixel array; and (iii) a write back circuitry, adapted to write back stored analog signals received from the first group to a second group of pixels located at a second location; whereas a relationship between the first and second locations is responsive to an estimated inter-image shift.
摘要翻译：本发明提供了一种用于提供图像的方法，所述方法包括：在中间曝光期间，将位于第一位置处的第一组像素曝光以提供表示光的模拟信号; 以及将模拟信号传送到位于第二位置的第二组像素; 而第一和第二位置之间的关系响应于估计的图像间移位; 然后进一步曝光第二组像素等。本发明提供了一种用于相机抖动补偿的装置，该装置包括：（i）二维阵列像素，而阵列的多个像素适于在中间曝光周期期间接收光并且响应于提供代表光的模拟信号; 并且还适于响应于代表先前接收到的光的右后卫的接收来改变其状况; （ii）模拟存储器，适于接收和存储代表光的模拟信号，所述模拟信号接收所述像素阵列内的第一组像素; 和（iii）写回电路，用于将存储的从第一组接收的模拟信号写回位于第二位置的第二组像素; 而第一和第二位置之间的关系响应于估计的图像间偏移。

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