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1. 发明授权

US08516292B2 Method and apparatus for providing symmetrical output data for a double data rate DRAM 失效
标题翻译：为双数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US08516292B2
公开(公告)日：2013-08-20
申请号：US13011191
申请日：2011-01-21
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G01F1/12
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

2. 发明申请

US20110119519A1 METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM 失效
标题翻译：用于为双向数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US20110119519A1
公开(公告)日：2011-05-19
申请号：US13011191
申请日：2011-01-21
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F1/12
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

3. 发明授权

US07421607B2 Method and apparatus for providing symmetrical output data for a double data rate DRAM 失效
标题翻译：为双数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US07421607B2
公开(公告)日：2008-09-02
申请号：US11751182
申请日：2007-05-21
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F13/42
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

4. 发明授权

US07877623B2 Method and apparatus for providing symmetrical output data for a double data rate DRAM 有权
标题翻译：为双数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US07877623B2
公开(公告)日：2011-01-25
申请号：US12222216
申请日：2008-08-05
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F13/42
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

5. 发明申请

US20090031158A1 Method and apparatus for providing symmetrical output data for a double data rate dram 有权
标题翻译：提供双数据速率的对称输出数据的方法和装置
公开(公告)号：US20090031158A1
公开(公告)日：2009-01-29
申请号：US12222216
申请日：2008-08-05
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F1/12
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

6. 发明授权

US07237136B2 Method and apparatus for providing symmetrical output data for a double data rate DRAM 失效
标题翻译：为双数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US07237136B2
公开(公告)日：2007-06-26
申请号：US10759077
申请日：2004-01-20
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F13/42
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

7. 发明授权

US06704881B1 Method and apparatus for providing symmetrical output data for a double data rate DRAM 失效
公开(公告)号：US06704881B1
公开(公告)日：2004-03-09
申请号：US09653409
申请日：2000-08-31
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F1342
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

8. 发明授权

US06316976B1 Method and apparatus for improving the performance of digital delay locked loop circuits 有权
标题翻译：用于提高数字延迟锁定环路电路性能的方法和装置
公开(公告)号：US06316976B1
公开(公告)日：2001-11-13
申请号：US09560848
申请日：2000-04-28
申请人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
发明人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
IPC分类号： H03L706
CPC分类号： H03L7/10 , H03K5/133 , H03L7/0814
摘要： A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.
摘要翻译：一种用于通过使用唯一的校正锁存器和新颖的复位机制电路来提高数字延迟锁定环（DDLL）的性能和精度的方法和装置，用于消除DDLL最小和最大延迟状态的不可操作性。通过使用三非门逻辑延迟元件设计，DDLL的精度进一步提高。根据本发明的DDLL在每个延迟线元件的输出处提供信号的对称上升沿和下降沿。根据本发明的DDLL进一步确保初始化时对随机值的不敏感性。此外，根据本发明的DDLL由于确保在相位检测操作期间实际的而不是分频的输入信号与输出信号之间的比较而提高了精度。

9. 发明授权

US6069506A Method and apparatus for improving the performance of digital delay locked loop circuits 失效
标题翻译：用于提高数字延迟锁定环路电路性能的方法和装置
公开(公告)号：US6069506A
公开(公告)日：2000-05-30
申请号：US81774
申请日：1998-05-20
申请人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
发明人： James E. Miller, Jr. , Aaron Schoenfeld , Manny Ma , R. Jacob Baker
IPC分类号： H03K5/13 , H03L7/081 , H03L7/10 , H03L7/06
CPC分类号： H03L7/10 , H03K5/133 , H03L7/0814
摘要： A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.
摘要翻译：一种用于通过使用唯一的校正锁存器和新颖的复位机制电路来提高数字延迟锁定环（DDLL）的性能和精度的方法和装置，用于消除DDLL最小和最大延迟状态的不可操作性。通过使用三非门逻辑延迟元件设计，DDLL的精度进一步提高。根据本发明的DDLL在每个延迟线元件的输出处提供信号的对称上升沿和下降沿。根据本发明的DDLL进一步确保初始化时对随机值的不敏感性。此外，根据本发明的DDLL由于确保在相位检测操作期间实际的而不是分频的输入信号与输出信号之间的比较而提高了精度。

10. 发明申请

US20060029173A1 Method and apparatus for output data synchronization with system clock in DDR 有权
标题翻译：用于与DDR系统时钟输出数据同步的方法和装置
公开(公告)号：US20060029173A1
公开(公告)日：2006-02-09
申请号：US11247496
申请日：2005-10-10
申请人： Wen Li , Aaron Schoenfeld
发明人： Wen Li , Aaron Schoenfeld
IPC分类号： H04L7/00
CPC分类号： H03L7/0812 , H03L7/0814 , H03L7/0818 , H03L7/087 , H03L7/107 , H04L7/033
摘要： A method and apparatus for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus is disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a system clock signal by delaying the system clock signal. A falling edge of the local timing signal is established and phase-locked to a falling edge of the system clock signal by further delaying only a portion of a signal representative of the delayed clock signal. By separately delaying different portions of the system clock signal and using the separately delayed portions to establish a local timing signal, a local timing signal may be established which is compensated for the varied effects of delay elements in a delay locked loop.
摘要翻译：一种用于大大减少或消除由延迟锁定环路中的延迟元件引起的定时偏移的方法和装置。公开了一种方法和装置，其中通过延迟系统时钟信号，建立本地定时信号的上升沿并锁相到系统时钟信号的上升沿。本地定时信号的下降沿通过进一步仅延迟表示延迟的时钟信号的信号的一部分而被建立并锁相到系统时钟信号的下降沿。通过分别延迟系统时钟信号的不同部分并且使用单独延迟的部分来建立本地定时信号，可以建立本地定时信号，其补偿延迟锁定环路中的延迟元件的变化的影响。

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