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1. 发明授权

US08127215B2 Signal loss detector for high-speed serial interface of a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口的信号丢失检测器
公开(公告)号：US08127215B2
公开(公告)日：2012-02-28
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03M13/03
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

2. 发明授权

US08111784B1 On-chip data signal eye monitoring circuitry and methods 有权
标题翻译：片上数据信号眼监测电路及方法
公开(公告)号：US08111784B1
公开(公告)日：2012-02-07
申请号：US12082483
申请日：2008-04-11
申请人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
IPC分类号： H04L25/06
CPC分类号： H04L25/063
摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.
摘要翻译：用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。这在眼部切片位置建立了眼睛的上限值。然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

3. 发明授权

US07821343B1 Transmitter with multiple phase locked loops 有权
标题翻译：具有多个锁相环的变送器
公开(公告)号：US07821343B1
公开(公告)日：2010-10-26
申请号：US12229813
申请日：2008-08-27
申请人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
发明人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03L7/23
摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.
摘要翻译：描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出或第二PLL的输出。在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。在宽范围模式下，需要较宽的频率范围。另一方面，在低抖动模式中，需要低抖动。

4. 发明授权

US08836443B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08836443B2
公开(公告)日：2014-09-16
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L23/66 , H03B5/08 , H03C3/22 , H01F27/29 , H03B5/12 , H01F27/28 , H01F21/12
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

5. 发明授权

US08184651B2 PLD architecture optimized for 10G Ethernet physical layer solution 有权
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：US08184651B2
公开(公告)日：2012-05-22
申请号：US12100360
申请日：2008-04-09
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

6. 发明申请

US20110235756A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20110235756A1
公开(公告)日：2011-09-29
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L27/06
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

7. 发明授权

US07759972B1 Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
标题翻译：具有异构高速串行接口电路的集成电路架构
公开(公告)号：US07759972B1
公开(公告)日：2010-07-20
申请号：US11981934
申请日：2007-10-31
申请人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。这些传统块离开设备的至少一个角落，不被这种遗留电路占用。这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

8. 发明授权

US08933751B1 High resolution capacitor 有权
标题翻译：高分辨率电容
公开(公告)号：US08933751B1
公开(公告)日：2015-01-13
申请号：US13475678
申请日：2012-05-18
申请人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
发明人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
IPC分类号： H03F3/45 , H01G4/40 , H03F1/56
CPC分类号： H01G4/40 , H01G17/00 , H03F1/56
摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
摘要翻译：具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。每个开关电容器包括开关电容器和串联耦合的开关。在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

9. 发明授权

US08319564B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08319564B2
公开(公告)日：2012-11-27
申请号：US12748261
申请日：2010-03-26
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H03B5/12 , H03L1/00
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

10. 发明授权

US08081723B1 Serial data signal eye width estimator methods and apparatus 有权
标题翻译：串行数据信号眼宽估计方法和装置
公开(公告)号：US08081723B1
公开(公告)日：2011-12-20
申请号：US12082343
申请日：2008-04-09
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H04L7/048 , H04L1/205 , H04L7/033
摘要： Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.
摘要翻译：用于确定高速串行数据信号的眼睛的至少部分宽度的方法和装置使用在该信号上操作的时钟和数据恢复电路，以产生与数据信号具有第一相位关系的第一时钟信号。第一时钟信号用于产生第二时钟信号，其相位可相对于第一相位被可控地偏移。第二时钟信号用于以不同量的相移对数据信号进行采样，例如直到错误检查电路检测到所得样本中的数据错误超过这种错误的可接受的阈值。引起超过阈值的相移量可用作测量眼睛宽度的基础。

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