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1. 发明申请

US20100164508A1 SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER 有权
标题翻译：用于测试结构的系统和方法
公开(公告)号：US20100164508A1
公开(公告)日：2010-07-01
申请号：US12616749
申请日：2009-11-11
申请人： WANG JIAN PING , Chin Chang Liao , Waisum Wong
发明人： WANG JIAN PING , Chin Chang Liao , Waisum Wong
IPC分类号： G01R31/02 , H01L23/48
CPC分类号： H01L22/30 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.
摘要翻译：晶圆上测试结构的系统和方法。根据实施例，本发明提供了一种用于测试芯片的测试结构。例如，测试结构和芯片在相同的基板材料上制造，并且正在进行的测试是在温度控制的环境中。测试结构包括位于芯片上方的顶部结构。例如，顶部结构可以由第一表面区域表征。顶部结构包括占据表面积的不到60％的第一金属材料。测试结构还包括位于芯片下方的底部结构。例如，底部结构可以由第二表面区域表征。第二表面积基本上等于第一表面积。底部结构包括第一硅材料。第一硅材料占据基本上所有的第二表面积。

2. 发明授权

US08415663B2 System and method for test structure on a wafer 有权
标题翻译：晶圆上测试结构的系统和方法
公开(公告)号：US08415663B2
公开(公告)日：2013-04-09
申请号：US12616749
申请日：2009-11-11
申请人： Wang Jian Ping , Chin Chang Liao , Waisum Wong
发明人： Wang Jian Ping , Chin Chang Liao , Waisum Wong
IPC分类号： H01L23/48
CPC分类号： H01L22/30 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area.
摘要翻译：晶圆上测试结构的系统和方法。根据实施例，本发明提供了一种用于测试芯片的测试结构。例如，测试结构和芯片在相同的基板材料上制造，并且正在进行的测试是在温度控制的环境中。测试结构包括位于芯片上方的顶部结构。例如，顶部结构可以由第一表面区域表征。顶部结构包括占据表面积的不到60％的第一金属材料。测试结构还包括位于芯片下方的底部结构。例如，底部结构可以由第二表面区域表征。第二表面积基本上等于第一表面积。底部结构包括第一硅材料。第一硅材料占据基本上所有的第二表面积。

3. 发明申请

US20070284663A1 SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS FABRICATED BY PROCESSES FOR MAKING CORE TRANSISTORS 有权
标题翻译：用于制造核心晶体管的工艺制成的多晶硅区域进行I / O ESD保护的系统和方法
公开(公告)号：US20070284663A1
公开(公告)日：2007-12-13
申请号：US11550529
申请日：2006-10-18
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/1041 , H01L29/105 , H01L29/402 , H01L29/42364 , H01L29/4238 , H01L29/7833
摘要： A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括耦合到第一系统并包括第一栅极的第一晶体管，位于第一栅极和第一衬底之间的第一介电层，第一源极和第一漏极。第一系统包括或耦合到核心晶体管，并且核心晶体管包括第二栅极，位于第二栅极和第二基板之间的第二介电层，第二源极和第二漏极。第一晶体管选自多个晶体管，并且多个晶体管包括多个栅极区域，多个源极区域和多个漏极区域。多个栅极区域中的每一个与多晶硅区域相交。

4. 发明授权

US08319286B2 System and method for input pin ESD protection with floating and/or biased polysilicon regions 有权
标题翻译：具有浮置和/或偏置多晶硅区域的输入引脚ESD保护的系统和方法
公开(公告)号：US08319286B2
公开(公告)日：2012-11-27
申请号：US12979306
申请日：2010-12-27
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L23/60 , H01L27/07
CPC分类号： H01L27/027
摘要： A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括第一晶体管，其包括第一漏极，包括第二漏极的第二晶体管和包括第一端子和第二端子的电阻器。第一端子耦合到第一漏极和第二漏极。另外，该系统包括耦合到第二终端的第三晶体管和受保护的系统。第三晶体管包括第一栅极，位于第一栅极和第一衬底之间的第一介电层，第一源极和第三漏极。受保护的系统包括第四晶体管，并且第四晶体管包括第二栅极，位于第二栅极和第二衬底之间的第二电介质层，第二源极和第四漏极。

5. 发明申请

US20120001261A1 SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR BIASED POLYSILICON REGIONS 有权
标题翻译：具有浮动和/或偏置多晶硅区域的输入引脚ESD保护的系统和方法
公开(公告)号：US20120001261A1
公开(公告)日：2012-01-05
申请号：US12979306
申请日：2010-12-27
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L23/60
CPC分类号： H01L27/027
摘要： A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括第一晶体管，其包括第一漏极，包括第二漏极的第二晶体管和包括第一端子和第二端子的电阻器。第一端子耦合到第一漏极和第二漏极。另外，该系统包括耦合到第二终端的第三晶体管和受保护的系统。第三晶体管包括第一栅极，位于第一栅极和第一衬底之间的第一介电层，第一源极和第三漏极。受保护的系统包括第四晶体管，并且第四晶体管包括第二栅极，位于第二栅极和第二衬底之间的第二电介质层，第二源极和第四漏极。

6. 发明授权

US08686507B2 System and method for I/O ESD protection with floating and/or biased polysilicon regions 有权
标题翻译：具有浮置和/或偏置多晶硅区域的I / O ESD保护的系统和方法
公开(公告)号：US08686507B2
公开(公告)日：2014-04-01
申请号：US11517546
申请日：2006-09-06
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括多个晶体管。多个晶体管包括多个栅极区域，多个源极区域和多个漏极区域。多个源极区域和多个漏极区域位于衬底中的有源区域内，并且有源区域与衬底中的至少一个隔离区域相邻。另外，该系统包括多晶硅区域。多晶硅区域通过电介质层与衬底分离，并且多晶硅区域与多个栅极区域中的每一个相交。多晶硅区域的至少一部分在有源区域上。

7. 发明授权

US08283726B2 System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors 有权
标题翻译：用于制造核心晶体管的工艺制造的具有多晶硅区域的I / O ESD保护的系统和方法
公开(公告)号：US08283726B2
公开(公告)日：2012-10-09
申请号：US12623363
申请日：2009-11-20
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/1041 , H01L29/105 , H01L29/402 , H01L29/42364 , H01L29/4238 , H01L29/7833
摘要： A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括耦合到第一系统并包括第一栅极的第一晶体管，位于第一栅极和第一衬底之间的第一介电层，第一源极和第一漏极。第一系统包括或耦合到核心晶体管，并且核心晶体管包括第二栅极，位于第二栅极和第二基板之间的第二介电层，第二源极和第二漏极。第一晶体管选自多个晶体管，并且多个晶体管包括多个栅极区域，多个源极区域和多个漏极区域。多个多晶硅区域设置在多个栅极区域中的至少一个附近。多个多晶硅区域与第一基板分离成多个电介质层。

8. 发明授权

US07642602B2 System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors 有权
标题翻译：用于制造核心晶体管的工艺制造的具有多晶硅区域的I / O ESD保护的系统和方法
公开(公告)号：US07642602B2
公开(公告)日：2010-01-05
申请号：US11550529
申请日：2006-10-18
申请人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
发明人： Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
IPC分类号： H01L21/8238
CPC分类号： H01L27/0266 , H01L29/1041 , H01L29/105 , H01L29/402 , H01L29/42364 , H01L29/4238 , H01L29/7833
摘要： A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.
摘要翻译：一种用于静电放电保护的系统和方法。该系统包括耦合到第一系统并包括第一栅极的第一晶体管，位于第一栅极和第一衬底之间的第一介电层，第一源极和第一漏极。第一系统包括或耦合到核心晶体管，并且核心晶体管包括第二栅极，位于第二栅极和第二基板之间的第二介电层，第二源极和第二漏极。第一晶体管选自多个晶体管，并且多个晶体管包括多个栅极区域，多个源极区域和多个漏极区域。多个栅极区域中的每一个与多晶硅区域相交。

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