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1. 发明专利

JP2006156998A Pattern generation method, manufacturing method for semiconductor device, semiconductor device, and program 有权
标题翻译：图形生成方法，半导体器件的制造方法，半导体器件和程序
公开(公告)号：JP2006156998A
公开(公告)日：2006-06-15
申请号：JP2005321571
申请日：2005-11-04
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： HATANO SHOSUKE , NISHIOKA TAKESHI , FUJIMAKI TAKESHI , OKAZAKI MOTOYA , WADA JUNICHI , KANEKO HISAFUMI , AZUMA KAZUYUKI , YOSHIDA KENJI , MATSUNAGA NORIAKI
IPC分类号： H01L21/3205 , G06F17/50 , H01L21/82 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a pattern generation method capable of increasing the pattern coverage rate of the peripheral region of an isolated pattern.
SOLUTION: After a wiring pattern arranged on an interlayer dielectric film and the wiring layout and hole layout of a hole pattern embedded in the interlayer dielectric film are obtained, the hole pattern is extracted, which is connected with the wiring pattern from the hole layout in a pattern processing region where the wiring pattern is arranged in the same wiring layer. A primary processing region is extracted so that the hole pattern may be included, and the pattern coverage rate of the wiring pattern included in the primary processing region is computed. After that, additional patterns are generated in the primary processing region based on the pattern coverage rate.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够提高隔离图案的周边区域的图案覆盖率的图案生成方法。解决方案：在布置在层间电介质膜上的布线图案和嵌入在层间电介质膜中的孔图案的布线布局和孔布局之后，提取孔图案，其与布线图案相连布线图案布置在同一布线层中的图案处理区域中的孔布局。提取主处理区域，使得可以包括空穴图案，并且计算包括在主处理区域中的布线图案的图案覆盖率。之后，基于模式覆盖率，在主处理区域中产生附加模式。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2004077283A Test and manufacturing method of semiconductor device 有权
公开(公告)号：JP2004077283A
公开(公告)日：2004-03-11
申请号：JP2002238032
申请日：2002-08-19
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： YOSHIDA KENJI , FUJIMAKI TAKESHI , NAKAZAWA HIROSHI , MIYAMOTO KOJI
IPC分类号： G01R31/30 , G01R31/28
CPC分类号： G01R31/2858 , G01R31/287
摘要： PROBLEM TO BE SOLVED: To provide a test method and a manufacturing method of a semiconductor device with reduced failure of Cu wirings occurring in the market.
SOLUTION: This method includes an accelerated test process for eliminating initial failure due to stress migration of wires occurring in a semiconductor device having wires made of copper or a copper alloy as the main component. The accelerated test process includes a stage for maintaining the temperature of the semiconductor device within a temperature range of plus and minus 40°C of a temperature for mostly accelerating the stress migration for 0.4 hour or longer.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2005142423A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005142423A
公开(公告)日：2005-06-02
申请号：JP2003378423
申请日：2003-11-07
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJIMAKI TAKESHI
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76816 , H01L21/76807 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device reduced in the generating rate of faulty disconnection in a conduction via due to stress migration, and to provide its manufacturing method. SOLUTION: The semiconductor device is provided with a multi-layer wiring structure which comprises a first wiring layer 13, a second interlayer insulating film 14 arranged on the first wiring layer 13, the conduction via 31 buried into a first via hole in the second interlayer insulating film 14 and whose lower end is contacted with the first wiring layer 13, a sacrifice via 32 buried into a second via hole in the second interlayer insulating film 14 and whose lower end is contacted with the first wiring layer 13 while the upper end thereof is in opened state electrically, and a second wiring layer 15 arranged at the vicinity of surface of the second interlayer insulating film 14 and connected to the upper end of the conduction via 31. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种降低由于应力迁移导致的通孔中的故障断开的发生率的半导体装置，并提供其制造方法。解决方案：半导体器件设置有多层布线结构，其包括布置在第一布线层13上的第一布线层13，第二层间绝缘膜14，埋入第一通孔中的导通孔31 第二层间绝缘膜14，其下端与第一布线层13接触，牺牲通孔32埋入第二层间绝缘膜14中的第二通孔中，并且其下端与第一布线层13接触，同时其上端处于打开状态，第二布线层15布置在第二层间绝缘膜14的表面附近并连接到导通通孔31的上端。（C）2005， JPO＆NCIPI

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