专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6037200A Compound semiconductor device and fabrication method 失效
标题翻译：复合半导体器件及其制造方法
公开(公告)号：US6037200A
公开(公告)日：2000-03-14
申请号：US39395
申请日：1998-03-16
申请人： Tomoya Uda , Akiyoshi Tamura
发明人： Tomoya Uda , Akiyoshi Tamura
IPC分类号： H01L21/265 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/423
CPC分类号： H01L29/66878 , H01L21/28581 , H01L21/28593 , H01L29/0891 , H01L29/42316 , H01L21/2654 , H01L21/26586
摘要： A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.
摘要翻译： WSi膜沉积在半绝缘GaAs衬底上。此后，形成第一Al掩模和第二SiO 2掩模，使得这两个掩模在WSi膜上重叠。使用含有大于20％的SF 6的气体的SF 6 / CF 4混合物来干法蚀刻WSi膜。 WSi膜是T形的，换句话说，WSi膜在横向长度上逐渐变窄。第二个面具被剥去。通过各向异性蚀刻工艺形成GAMMA形栅电极。随后，进行各向同性蚀刻处理以将电极的栅极长度减小到0.5μm或更小。植入硅离子以形成单独的n'层。通过膜被沉积。植入硅离子以形成单独的n +层。

2. 发明授权

US5994728A Field effect transistor and method for producing the same 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US5994728A
公开(公告)日：1999-11-30
申请号：US748983
申请日：1996-11-14
申请人： Tomoya Uda , Akiyoshi Tamura
发明人： Tomoya Uda , Akiyoshi Tamura
IPC分类号： H01L21/285 , H01L21/338 , H01L29/812 , H01L29/72
CPC分类号： H01L29/66863 , H01L21/28581 , H01L29/812
摘要： A method for producing a field effect transistor includes: a first step of forming an insulating film over a substrate; a second step of dry etching the insulating film to form a rectangular insulating pattern having side surfaces; a third step of forming a gate electrode film over the substrate having the rectangular insulating pattern; a fourth step of conducting substantially anisotropic etching of the gate electrode film to form side walls made of the gate electrode film adjacent to the side surfaces of the rectangular insulating pattern; and a fifth step of removing at least a portion of the insulating pattern to form a side wall gate.
摘要翻译：一种场效应晶体管的制造方法，包括：在基板上形成绝缘膜的第一工序; 干法蚀刻绝缘膜以形成具有侧表面的矩形绝缘图案的第二步骤; 在具有矩形绝缘图案的基板上形成栅电极膜的第三步骤; 进行栅极电极膜的大致各向异性蚀刻以形成由邻近矩形绝缘图案的侧表面的栅极电极膜制成的侧壁的第四步骤; 以及除去绝缘图案的至少一部分以形成侧壁浇口的第五步骤。

3. 发明授权

US5907177A Semiconductor device having a tapered gate electrode 失效
标题翻译：具有锥形栅电极的半导体器件
公开(公告)号：US5907177A
公开(公告)日：1999-05-25
申请号：US614492
申请日：1996-03-13
申请人： Tomoya Uda , Akiyoshi Tamura
发明人： Tomoya Uda , Akiyoshi Tamura
IPC分类号： H01L21/265 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/423 , H01L29/76 , H01L31/0328
CPC分类号： H01L29/66878 , H01L21/28581 , H01L21/28593 , H01L29/0891 , H01L29/42316 , H01L21/2654 , H01L21/26586
摘要： A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.
摘要翻译： WSi膜沉积在半绝缘GaAs衬底上。此后，形成第一Al掩模和第二SiO 2掩模，使得这两个掩模在WSi膜上重叠。使用含有大于20％的SF 6的气体的SF 6 / CF 4混合物来干法蚀刻WSi膜。 WSi膜是T形的，换句话说，WSi膜在横向长度上逐渐变窄。第二个面具被剥去。通过各向异性蚀刻工艺形成GAMMA形栅电极。随后，进行各向同性蚀刻处理以将电极的栅极长度减小到0.5μm或更小。植入硅离子以形成单独的n'层。通过膜被沉积。植入硅离子以形成单独的n +层。

4. 发明授权

US5824575A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5824575A
公开(公告)日：1998-10-20
申请号：US517854
申请日：1995-08-22
申请人： Hiromasa Fujimoto , Hiroyuki Masato , Yorito Ota , Tomoya Uda
发明人： Hiromasa Fujimoto , Hiroyuki Masato , Yorito Ota , Tomoya Uda
IPC分类号： H01L21/338 , H01L29/10 , H01L29/808 , H01L29/812
CPC分类号： H01L29/66863 , H01L29/1029 , H01L29/1058 , H01L29/66878 , H01L29/808 , H01L29/812 , H01L29/8128
摘要： After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.
摘要翻译：在形成n型有源层之后，沉积在GaAs衬底，氧化硅膜和氮化硅膜的预定区域处的n +型源极区域和n +型漏极区域，然后形成源极和漏极电极。通过使用形成在氮化硅膜上的抗蚀剂掩模对氮化硅膜进行过蚀刻，去除在栅电极形成区域处的氧化硅膜的上层部分，并且在栅电极正下方的有源层上的载流子浓度降低了。这提高了栅/漏击穿电压。此后，通过湿蚀刻除去栅极形成区域处的氧化硅膜的下层部分，并且在该去除区域处形成栅电极。由于仅在栅电极正下方的有源层的表面区域减小载流子浓度，所以提高了漏极击穿电压。

5. 发明授权

US06232159B1 Method for fabricating compound semiconductor device 有权
标题翻译：化合物半导体器件的制造方法
公开(公告)号：US06232159B1
公开(公告)日：2001-05-15
申请号：US09357828
申请日：1999-07-21
申请人： Tomoya Uda
发明人： Tomoya Uda
IPC分类号： H01L21338
CPC分类号： H01L29/66462
摘要： A method for fabricating a compound semiconductor device according to the present invention includes the steps of: a) depositing a first compound semiconductor layer over a substrate; b) depositing a second compound semiconductor layer on the first compound semiconductor layer, the second compound semiconductor layer being made of a compound with etch properties different from those of a compound for the first compound semiconductor layer; c) forming an etching mask on the second compound semiconductor layer, the etching mask having a first opening; d) anisotropically dry-etching the second compound semiconductor layer selectively with respect to the first compound semiconductor layer through the etching mask, thereby forming a second opening in the second compound semiconductor layer; and e) isotropically dry-etching the second compound semiconductor layer selectively with respect to the first compound semiconductor layer through the etching mask, thereby side-etching a side of the second opening and making the second opening greater in size than the first opening.
摘要翻译：根据本发明的制备化合物半导体器件的方法包括以下步骤：a）在衬底上沉积第一化合物半导体层; b）在所述第一化合物半导体层上沉积第二化合物半导体层，所述第二化合物半导体层由具有不同于所述第一化合物半导体层的化合物的蚀刻性质的化合物制成; c）在所述第二化合物半导体层上形成蚀刻掩模，所述蚀刻掩模具有第一开口; d）通过蚀刻掩模，相对于第一化合物半导体层选择性地对第二化合物半导体层进行各向异性干蚀刻，从而在第二化合物半导体层中形成第二开口; 以及e）通过所述蚀刻掩模，相对于所述第一化合物半导体层选择性地对所述第二化合物半导体层进行各向异性干蚀刻，从而侧蚀所述第二开口的一侧，并使所述第二开口的尺寸大于所述第一开口的大小。

6. 发明授权

US06376898B1 Bipolar transistor layout with minimized area and improved heat dissipation 有权
标题翻译：双极晶体管布局，最小面积和更好的散热
公开(公告)号：US06376898B1
公开(公告)日：2002-04-23
申请号：US09631104
申请日：2000-08-01
申请人： Tomoya Uda , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara
发明人： Tomoya Uda , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara
IPC分类号： H01L2973
CPC分类号： H01L29/0692 , H01L27/0207 , H01L27/082 , H01L29/737
摘要： An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively, which are adjacent to each other. The second transistor is closer to the first transistor than any other transistor in the second bank.
摘要翻译：本发明的半导体集成电路器件包括在衬底上的多个晶体管组。这些堤被布置成在设备的平面布局中彼此基本平行。每个所述存储体包括多个单元晶体管，每个单元晶体管包括基极，发射极和集电极。在器件的平面布局中，晶体管中的第一个晶体管的位置沿着两个晶体管延伸的方向从第二晶体管的位置移位。第一和第二晶体管分别属于彼此相邻的第一和第二晶体管。第二晶体管比第二组中的任何其它晶体管更靠近第一晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式