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1. 发明授权

US6115834A Method for quickly identifying floating cells by a bit-line coupling pattern (BLCP) 有权
标题翻译：通过位线耦合模式（BLCP）快速识别浮动单元的方法
公开(公告)号：US6115834A
公开(公告)日：2000-09-05
申请号：US146042
申请日：1998-09-02
申请人： Tean-Sen Jen , Shiou-Yu Wang , Wu-Der Yang , Chang-Pin Chen
发明人： Tean-Sen Jen , Shiou-Yu Wang , Wu-Der Yang , Chang-Pin Chen
IPC分类号： G11C29/10 , G11C29/00 , G11C7/00
CPC分类号： G11C29/10
摘要： A method for quickly identifying floating cells by a bit-line coupling pattern (BLCP), an electronic analysis method, identifies floating cells by inputting different background data and inducing net charges from adjacent bit-lines to the bit-lines corresponding to floating cells by coupling parasitic capacitors, wherein the floating results from open bit-line contacts and/or open DRAM cell contacts. Moreover, a method for identifying floating cells according to the invention has the advantages of high efficiency and low cost.
摘要翻译：一种通过电子分析方法通过位线耦合模式（BLCP）快速识别浮动单元的方法，通过输入不同的背景数据并通过相应于浮动单元的位线的相邻位线引起净电荷来识别浮动单元，耦合寄生电容器，其中来自开放位线触点和/或开放DRAM单元触点的浮动。此外，根据本发明的用于识别浮动细胞的方法具有效率高，成本低的优点。

2. 发明授权

US06057187A DRAM structure with multiple memory cells sharing the same bit-line contact and fabrication method thereof 有权
标题翻译：具有共享相同位线接触的多个存储单元的DRAM结构及其制造方法
公开(公告)号：US06057187A
公开(公告)日：2000-05-02
申请号：US164354
申请日：1998-10-01
申请人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
发明人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
IPC分类号： H01L27/108 , H10L21/8242
CPC分类号： H01L27/10805 , H01L27/10808 , Y10S257/904 , Y10S257/906
摘要： The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.
摘要翻译：本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。

3. 发明授权

US5989952A Method for fabricating a crown-type capacitor of a DRAM cell 失效
标题翻译：制造DRAM单元的冠型电容器的方法
公开(公告)号：US5989952A
公开(公告)日：1999-11-23
申请号：US934617
申请日：1997-09-22
申请人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng , Chi-Hui Lin
发明人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng , Chi-Hui Lin
IPC分类号： C12Q1/48 , H01L21/02 , H01L21/8242 , H01L12/8242
CPC分类号： H01L28/92 , C12Q1/48 , H01L27/10852
摘要： A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.
摘要翻译：公开了一种在半导体衬底上制造具有冠型电容器的DRAM单元的方法。该方法包括以下步骤：（a）在半导体衬底上形成晶体管; （b）在所述晶体管上形成绝缘层; （c）选择性地蚀刻绝缘层以形成接触开口; （d）在所述绝缘层上形成第一导电层并填充到所述接触开口中; （e）在所述第一导电层上形成蚀刻停止层和掩模层; （f）图案掩模层以形成多个开口; （g）在掩模层的侧壁上形成电介质间隔物，去除蚀刻停止层的暴露部分; （h）通过使用电介质间隔物作为掩模，各向异性地蚀刻掩模层和第一导电层，分别暴露蚀刻停止层和绝缘层; （i）去除未覆盖的蚀刻停止层以暴露第一导电层; （j）通过使用电介质间隔物作为掩模，将第一导电层各向异性蚀刻到预定深度，由此形成冠型存储电极; （k）去除电介质间隔物和蚀刻停止层; （l）在所述存储电极的暴露部分上形成介电层; 和（m）在所述电介质层上形成作为相对电极的第二导电层。

4. 发明授权

US5955757A Dram structure with multiple memory cells sharing the same bit-line contact 失效
标题翻译：具有多个存储单元共享相同位线触点的Dram结构
公开(公告)号：US5955757A
公开(公告)日：1999-09-21
申请号：US54547
申请日：1998-04-03
申请人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
发明人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10808 , Y10S257/904 , Y10S257/906
摘要： The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.
摘要翻译：本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。

5. 发明授权

US06403418B2 Method of fabricating cup-shape cylindrical capacitor of high density DRAMs 有权
标题翻译：制造高密度DRAM的杯形圆柱形电容器的方法
公开(公告)号：US06403418B2
公开(公告)日：2002-06-11
申请号：US09551535
申请日：2000-04-18
申请人： Shiou-Yu Wang , Jia-Shyong Cheng , Tean-Sen Jen , Ming-Teng Hsieh
发明人： Shiou-Yu Wang , Jia-Shyong Cheng , Tean-Sen Jen , Ming-Teng Hsieh
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3143 , H01L21/31604 , H01L27/10855
摘要： A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.
摘要翻译：公开了一种制造高密度动态随机存取存储器（DRAM）单元的杯形圆柱形电容器的方法。杯状电容器形状通过首先在硅衬底上沉积第一多晶硅层来实现; 然后通过常规的光刻和蚀刻技术形成覆盖第一多晶硅层和限定的第三介电冠的第三介电层; 沉积覆盖第三介电冠和第一多晶硅层的第二多晶硅层; 然后第一多晶硅和第二多晶硅层垂直各向异性回蚀以限定圆柱形电容器的存储节点; 去除第三介质冠; 最后，电容器的电容器电介质层和多晶硅顶板形成为完成用于高密度DRAM应用的杯形圆柱形电容器形成。

6. 发明授权

US06337173B2 Method for fabricating a semiconductor capacitor 有权
标题翻译：半导体电容器的制造方法
公开(公告)号：US06337173B2
公开(公告)日：2002-01-08
申请号：US09208452
申请日：1998-12-10
申请人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
发明人： Tean-Sen Jen , Shiou-Yu Wang , Jia-Shyong Cheng
IPC分类号： G03F726
CPC分类号： H01L28/92 , H01L21/76213 , H01L27/10852
摘要： A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.
摘要翻译：一种在半导体衬底上制造电容器电极的方法包括以下步骤：在半导体衬底上形成导电层; 在所述导电层上形成光致抗蚀剂层; 通过干涉曝光步骤图案化光致抗蚀剂层; 并使用图案化的光致抗蚀剂层作为掩模图案化导电层，从而形成电容器电极。

7. 发明授权

US06180993B2 Ion repulsion structure for fuse window 有权
标题翻译：保险丝窗的离子排斥结构
公开(公告)号：US06180993B2
公开(公告)日：2001-01-30
申请号：US09153870
申请日：1998-09-15
申请人： Shiou-Yu Wang , Tean-Sen Jen
发明人： Shiou-Yu Wang , Tean-Sen Jen
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An ion repulsion structure for a fuse window is provided. The ion repulsion structure includes multi-level metallic layers and a P-type silicon semiconductor substrate having a plurality of wells. The P-type silicon semiconductor substrate includes an N-type well, a P-type well formed in the N-type well and a plurality of P+ type diffusion regions formed in the P-type well. A fuse element is formed on the P-type silicon semiconductor substrate. A fuse window layer is formed over the fuse element. Multi-level metallic layers surrounding the fuse window are formed. A plurality of contact plugs is electrically connected between the P+ type diffusion regions of the semiconductor substrate and the lowest metallic layer. A plurality of via plugs electrically connect the multi-level metallic layers to each other.
摘要翻译：提供了一种用于保险丝窗的离子排斥结构。离子斥力结构包括多层金属层和具有多个阱的P型硅半导体衬底。 P型硅半导体衬底包括N型阱，在N型阱中形成的P型阱以及形成在P型阱中的多个P +型扩散区。在P型硅半导体基板上形成熔丝元件。保险丝窗口层形成在保险丝元件上。形成围绕保险丝窗的多层金属层。多个接触插塞电连接在半导体衬底的P +型扩散区和最下层的金属层之间。多个通孔塞将多层金属层彼此电连接。

8. 发明授权

US5923989A Method of fabricating rugged capacitor of high density DRAMs 失效
标题翻译：制造高密度DRAM耐久电容器的方法
公开(公告)号：US5923989A
公开(公告)日：1999-07-13
申请号：US81598
申请日：1998-05-20
申请人： Shian-Jyh Lin , Tsu-An Lin , Wen-Chieh Chang , Shiou-Yu Wang , Tean-Sen Jen , Hui-Jen Yang , Jia-Shyong Cheng , Ming-Teng Hsieh
发明人： Shian-Jyh Lin , Tsu-An Lin , Wen-Chieh Chang , Shiou-Yu Wang , Tean-Sen Jen , Hui-Jen Yang , Jia-Shyong Cheng , Ming-Teng Hsieh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers. Next, the polysilicon layer is anisotropically etched by using the rugged polysilicon layer as an etching mask to transfer rugged surface profile from the rugged polysilicon layer to the polysilicon layer. Finally, an interelectrode dielectric layer and a third polysilicon layer as top electrodes of the capacitors are sequentially formed to complete the rugged capacitor for high density DRAM applications.
摘要翻译：公开了一种制造高密度动态随机存取存储器（DRAM）单元的坚固电容器结构的方法。首先，在半导体硅衬底上形成MOSFET，字线和位线。接下来，在整个硅衬底上依次沉积介电层和掺杂多晶硅层。然后将电介质层和掺杂多晶硅层部分地蚀刻到开源接触窗口。然后，沉积覆盖掺杂多晶硅层并填充到源极接触窗口中的多晶硅层。接下来，部分蚀刻多晶硅层和掺杂多晶硅层以限定电容器的底部电极。接下来，进行倾斜角注入以将杂质植入多晶硅层的顶表面和四个侧壁以及掺杂多晶硅层。接下来，沉积覆盖多晶硅，掺杂多晶硅和第三介电层的坚固的多晶硅层。接下来，通过使用坚固的多晶硅层作为蚀刻掩模来将多晶硅层各向异性地蚀刻，以将粗糙的表面轮廓从坚固的多晶硅层转移到多晶硅层。最后，依次形成作为电容器顶电极的电极间电介质层和第三多晶硅层，以完成用于高密度DRAM应用的坚固电容器。

9. 发明授权

US06320416B1 Input buffer means for high voltage operation 有权
标题翻译：输入缓冲装置用于高压运行
公开(公告)号：US06320416B1
公开(公告)日：2001-11-20
申请号：US09289654
申请日：1999-04-12
申请人： Ming-Shiang Wang , Tean-Sen Jen , C. B. Chen , Shih-Hsun Liang , Shiou-Yu Wang
发明人： Ming-Shiang Wang , Tean-Sen Jen , C. B. Chen , Shih-Hsun Liang , Shiou-Yu Wang
IPC分类号： H03K1900
CPC分类号： H03K3/356139 , H03K17/102
摘要： An input buffer capable of high voltage operation includes a transmission gate connected to a boosting voltage source. The input buffer can be used to maintain the processing speed and noise margin of a digital circuit even through the input voltage thereof is excessively high. Moreover, the input buffer can be used in an address latch or inverter-type circuit.
摘要翻译：能够进行高压操作的输入缓冲器包括连接到升压电压源的传输门。即使输入电压过高，也可以使用输入缓冲器来保持数字电路的处理速度和噪声容限。此外，输入缓冲器可用于地址锁存器或逆变器型电路。

10. 发明授权

US5966610A Method of fabricating capacitor plate 失效
标题翻译：制造电容器板的方法
公开(公告)号：US5966610A
公开(公告)日：1999-10-12
申请号：US2675
申请日：1998-01-05
申请人： Shiou-Yu Wang , Tean-Sen Jen , Jia-Shyong Cheng
发明人： Shiou-Yu Wang , Tean-Sen Jen , Jia-Shyong Cheng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L28/92 , H01L28/91 , H01L27/10814 , H01L27/10852
摘要： A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed. The remaining conducting layer and the conducting spacers constitute the capacitor's bottom electrode plate.
摘要翻译：构成电容器板的方法首先构成基板。然后，在基板上形成第一绝缘层。顺序地，在第一绝缘层上形成缓冲层和构成堆叠结构的第二绝缘层。接下来，将堆叠结构图案化成开口，从而使第一绝缘层的一部分暴露于其中。随后，在开口的侧壁上形成导电间隔物。此后除去第二绝缘层，同时将不被缓冲层和导电间隔物覆盖的第一绝缘层的一部分移除以形成接触窗，从而使基板的一部分暴露。然后，将导电层顺应地沉积在衬底上，然后蚀刻掉直到缓冲层的一部分露出。最后，暴露的缓冲层被去除。剩余的导电层和导电间隔物构成电容器的底部电极板。

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