专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110249503A1 SELECT GATE PROGRAMMING IN A MEMORY DEVICE 有权
标题翻译：在存储器中选择编程
公开(公告)号：US20110249503A1
公开(公告)日：2011-10-13
申请号：US12756366
申请日：2010-04-08
申请人： Shigekazu Yamada , Aaron Yip
发明人： Shigekazu Yamada , Aaron Yip
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C16/102 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
摘要翻译：公开了用于编程选择门，存储器件和存储器系统的方法。在一种用于编程的方法中，程序禁止电压从源极线传送到未选位线。在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

2. 发明授权

US08542534B2 Select gate programming in a memory device 有权
标题翻译：在存储设备中选择门编程
公开(公告)号：US08542534B2
公开(公告)日：2013-09-24
申请号：US12756366
申请日：2010-04-08
申请人： Shigekazu Yamada , Aaron Yip
发明人： Shigekazu Yamada , Aaron Yip
IPC分类号： G11C11/34
CPC分类号： G11C16/102 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
摘要翻译：公开了用于编程选择门，存储器件和存储器系统的方法。在一种用于编程的方法中，程序禁止电压从源极线传送到未选位线。在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

3. 发明授权

US08238165B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US08238165B2
公开(公告)日：2012-08-07
申请号：US13007361
申请日：2011-01-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

4. 发明授权

US07920428B2 Methods and apparatuses relating to automatic cell threshold voltage measurement 有权
标题翻译：与自动电池阈值电压测量相关的方法和装置
公开(公告)号：US07920428B2
公开(公告)日：2011-04-05
申请号：US12352147
申请日：2009-01-12
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C29/50 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C29/12005 , G11C29/50004
摘要： Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current generator, a plurality of memory cells and a bit line pre-charge reference circuit. If the reference current is greater than the memory cell current, the bit line voltage will increase. Conversely, if the reference current is less than the memory cell current, the bit line voltage will decrease. The reference current is generated in large steps until a comparator, that compares the bit line voltage and a bit line pre-charge reference voltage, is switched. The reference current then generates a current in small steps until the comparator is again switched. The reference current converges on the memory cell current within an accuracy of 10 nA. The memory cell threshold voltage is then determined from the memory cell current. Systems including memory according to an embodiment of the invention are also disclosed.
摘要翻译：公开了用于自动测量存储单元阈值电压的方法和装置。测量电路包括内部参考电流发生器，多个存储器单元和位线预充电参考电路。如果参考电流大于存储单元电流，则位线电压将增加。相反，如果参考电流小于存储单元电流，则位线电压将降低。参考电流以很大的步长产生，直到比较位线电压和位线预充电参考电压的比较器被切换为止。参考电流然后以小步骤产生电流，直到再次切换比较器。参考电流在10 nA的精度内收敛于存储单元电流。然后从存储单元电流确定存储单元阈值电压。还公开了包括根据本发明的实施例的存储器的系统。

5. 发明授权

US07800953B2 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices 有权
标题翻译：用于在编程或擦除非易失性存储器件期间选择性地限制峰值功耗的方法和系统
公开(公告)号：US07800953B2
公开(公告)日：2010-09-21
申请号：US12505909
申请日：2009-07-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

6. 发明申请

US20090238011A1 VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE 有权
标题翻译：内存数据寄存器内的VCC控制
公开(公告)号：US20090238011A1
公开(公告)日：2009-09-24
申请号：US12052271
申请日：2008-03-20
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device.
摘要翻译：提供了一种包括耦合到数据寄存器内的第一反相器的限流电路的存储器件。限流电路控制提供给第一反相器的电压，并且可以调整参考电压，使得防止提供给第一反相器的电压降到低于提供给数据寄存器内的第二反相器的电压。存储器件可以包括开关，以允许耦合到限流电路以编程存储器件。

7. 发明申请

US20090180333A1 Semiconductor memory column decoder device and method 有权
标题翻译：半导体存储器列解码器装置及方法
公开(公告)号：US20090180333A1
公开(公告)日：2009-07-16
申请号：US12008417
申请日：2008-01-10
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

8. 发明申请

US20080117686A1 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile memory devices 有权
标题翻译：用于在编程或擦除非易失性存储器件期间选择性地限制峰值功耗的方法和系统
公开(公告)号：US20080117686A1
公开(公告)日：2008-05-22
申请号：US11601368
申请日：2006-11-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C5/14
CPC分类号： G11C16/30 , G11C16/0483
摘要： A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the memory cells. The power supply circuit includes a reference current source supplying a reference current having a predetermined magnitude. The reference current source is coupled to a current generator, which supplies current to the array. The current generator may use current mirrors, and it supplies a current to the array having a predetermined relationship to the reference current. The current generator is selectively enabled by a control circuit so that current is supplied to the array during programming or erasing of at least some of the memory cells in the array.
摘要翻译：电源电路用于在存储器单元的编程或擦除期间向非易失性存储单元阵列提供具有有限峰值幅度的功率。电源电路包括提供具有预定大小的参考电流的参考电流源。参考电流源耦合到电流发生器，其向阵列提供电流。电流发生器可以使用电流镜，并且它向阵列提供与参考电流具有预定关系的电流。电流发生器由控制电路选择性地使能，使得在阵列中的至少一些存储器单元的编程或擦除期间将电流提供给阵列。

9. 发明授权

US07227778B2 Semiconductor device and writing method 有权
标题翻译：半导体器件和写入方法
公开(公告)号：US07227778B2
公开(公告)日：2007-06-05
申请号：US11194023
申请日：2005-07-29
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted into information according to each level of the multi-level memory cell, a write circuit writing information into the multi-level memory cell on a group basis corresponding to the number of memory cells simultaneously programmable, according to the write information, and a control circuit controlling programming the memory cell array. The information is simultaneously programmed on the group basis into which multiple-word input information is divided, and makes it possible to shorten a program period substantially on a word basis. The program period is not increased, even if programming and verification are repeated several times in programming the multi-level memory cell.
摘要翻译：一种半导体器件具有存储单元阵列，该存储单元阵列包括具有多个和不同阈值的多电平存储单元，第一锁存电路锁存多字输入信息的信息，第二锁存电路锁存写信息，根据多级存储器单元的每个级别将输入信息的字转换为信息，写电路根据与可同时编程的存储单元的数量对应的组，将信息写入多级存储器单元，根据写入信息，以及控制对存储单元阵列进行编程的控制电路。该信息同时被编程在分组多字输入信息的组基础上，并且使得可以基本上基于单词缩短程序周期。即使编程和验证在编程多层存储单元中重复多次，程序周期也不会增加。

10. 发明申请

US20060002200A1 Voltage control circuit and semiconductor device 有权
标题翻译：电压控制电路和半导体器件
公开(公告)号：US20060002200A1
公开(公告)日：2006-01-05
申请号：US11166575
申请日：2005-06-24
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/00
CPC分类号： G11C16/30 , G11C5/14 , H02M3/07
摘要： A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node.
摘要翻译：电压控制电路包括电容器，分别提供给电容器并选择性地将电容器与给定节点耦合的第一开关以及分别设置在第一开关和给定节点之间并且选择性地将第一开关连接到给定节点的第二开关节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式