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1. 发明授权

US07898853B2 Multi-bit data memory system and read operation 有权
标题翻译：多位数据存储系统和读操作
公开(公告)号：US07898853B2
公开(公告)日：2011-03-01
申请号：US12204860
申请日：2008-09-05
申请人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
发明人： Seung-Jae Lee , Dong-Ku Kang , Seung-Hwan Song , Jun-Jin Kong , Dong-Hyuk Chae , Sung-Chung Park
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/3418
摘要： Provided is a read operation for a N-bit data non-volatile memory system. The method includes determining in relation to data states of adjacent memory cells associated with a selected memory cell in the plurality of memory cells whether read data obtained from the selected memory cell requires compensation, and if the read data requires compensation, replacing the read data with compensated read data.
摘要翻译：提供了一种用于N位数据非易失性存储器系统的读取操作。该方法包括：确定与多个存储器单元中的所选存储单元相关联的相邻存储器单元的数据状态，从所选择的存储器单元获得的读取数据是否需要补偿，以及如果读取的数据需要补偿，则用补偿读数据。

2. 发明申请

US20090164710A1 SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF 审中-公开
标题翻译：半导体存储器系统及其访问方法
公开(公告)号：US20090164710A1
公开(公告)日：2009-06-25
申请号：US12340846
申请日：2008-12-22
申请人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
发明人： Jin-Hyeok Choi , Duck-Hyun Chang , Jun-Jin Kong , Dong-Hyuk Chae , Seung-Jae Lee , Dong-Ku Kang
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/20 , G11C16/10
摘要： A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.
摘要翻译：半导体存储器系统及其访问方法。半导体存储器系统包括非易失性存储器和存储器控制器。非易失性存储器将监视数据存储在多个存储单元中的一个或多个中。存储器控制器控制非易失性存储器。存储器控制器根据检测结果检测监视数据并调整提供给多个存储单元的偏置电压。

3. 发明申请

US20100277979A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20100277979A1
公开(公告)日：2010-11-04
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

4. 发明授权

US07791938B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US07791938B2
公开(公告)日：2010-09-07
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

5. 发明授权

US08208298B2 MSB-based error correction for flash memory system 有权
标题翻译：基于MSB的闪存系统的纠错
公开(公告)号：US08208298B2
公开(公告)日：2012-06-26
申请号：US12836249
申请日：2010-07-14
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

6. 发明申请

US20090016103A1 MSB-BASED ERROR CORRECTION FOR FLASH MEMORY SYSTEM 有权
标题翻译：用于闪存存储器系统的基于MSB的错误校正
公开(公告)号：US20090016103A1
公开(公告)日：2009-01-15
申请号：US12169109
申请日：2008-07-08
申请人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
发明人： Dong-Ku Kang , Seung-Jae Lee , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C2029/0411
摘要： A flash memory system includes a multi-bit flash memory device having a memory cell array including memory cells arranged in rows and columns; a read circuit configured to read data from the memory cell array; and control logic configured to control the read circuit so as to successively read data from a selected memory cell and adjacent memory cells to the selected memory cell in response to a request for a read operation with respect to MSB data stored in the selected memory cell. A compare circuit is configured to compare data read from the adjacent memory cells to the selected memory cell provided from the multi-bit flash memory device and to correct data read from the selected memory cells based upon the comparison result.
摘要翻译：闪存系统包括具有存储单元阵列的多位闪存器件，该存储器单元阵列包括以行和列排列的存储器单元; 读取电路，被配置为从存储单元阵列读取数据; 以及控制逻辑，被配置为控制所述读取电路，以便响应于对存储在所选择的存储器单元中的MSB数据的读取操作的请求，连续地将数据从所选择的存储器单元和相邻存储器单元读取到所选择的存储器单元。比较电路被配置为将从相邻存储器单元读取的数据与从多位闪存器件提供的所选择的存储器单元进行比较，并且基于比较结果校正从所选存储器单元读取的数据。

7. 发明授权

US08274840B2 Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法
公开(公告)号：US08274840B2
公开(公告)日：2012-09-25
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

8. 发明申请

US20100091578A1 Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
标题翻译：在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同
公开(公告)号：US20100091578A1
公开(公告)日：2010-04-15
申请号：US12498508
申请日：2009-07-07
申请人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
发明人： Yong-June Kim , Jae-Hong Kim , Kyoung-Lae Cho , Seung-Hwan Song , Jun-Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/16
摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
摘要翻译：非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控制器。存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

9. 发明授权

US09069714B2 Device including an external memory connection unit capable of adopting an external memory 有权
标题翻译：装置包括能够采用外部存储器的外部存储器连接单元
公开(公告)号：US09069714B2
公开(公告)日：2015-06-30
申请号：US13606551
申请日：2012-09-07
申请人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
发明人： Hak-Soo Yu , Jun-Jin Kong , Hyoung-Joon Kim , Joo-Young Hwang , In-Su Choi
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F13/16 , G06F13/1694 , G06F13/385
摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.
摘要翻译：设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。内部存储器可以通过存储器总线直接连接到存储器控制器。外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

10. 发明授权

US08522124B2 Semiconductor device and decoding method thereof 有权
标题翻译：半导体器件及其解码方法
公开(公告)号：US08522124B2
公开(公告)日：2013-08-27
申请号：US13069834
申请日：2011-03-23
申请人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
发明人： Yong-June Kim , Jun-Jin Kong , Young-Hwan Lee , Jae-Hong Kim
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1048
摘要： An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.
摘要翻译：错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。第二解码器连接到第一解码器。第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

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