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1. 发明申请

US20140032801A1 METHOD AND APPARATUS FOR ON-CHIP DEBUGGING 有权
标题翻译：用于片上调试的方法和装置
公开(公告)号：US20140032801A1
公开(公告)日：2014-01-30
申请号：US13557756
申请日：2012-07-25
申请人： Scott P. Nixon , Tiger Lu Lu , Eric M. Rentschler
发明人： Scott P. Nixon , Tiger Lu Lu , Eric M. Rentschler
IPC分类号： G06F13/00
CPC分类号： G06F11/364 , G06F11/3648
摘要： The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.
摘要翻译：本发明提供一种用于动态配置调试触发模式的方法和装置。该方法的一个示例性实施例包括比较在总线的多条线路的第一子集上接收的比特值与第一比特模式，并响应于在总线的多条线路的第二子集上接收的比特值比较指示在第一子集上接收的比特的值与第一种比特模式相匹配。该方法的示例性实施例还包括使用捕获的值定义用于触发调试动作的第二模式。

2. 发明授权

US08959398B2 Multiple clock domain debug capability 有权
标题翻译：多个时钟域调试功能
公开(公告)号：US08959398B2
公开(公告)日：2015-02-17
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译：具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值，以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。

3. 发明授权

US09442815B2 Distributed on-chip debug triggering with allocated bus lines 有权
标题翻译：分配的片上调试触发与分配的总线
公开(公告)号：US09442815B2
公开(公告)日：2016-09-13
申请号：US13665719
申请日：2012-10-31
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/36 , G06F11/27 , G06F11/30 , G06F11/34
CPC分类号： G06F11/27 , G06F11/3065 , G06F11/348 , G06F11/3648 , G06F11/3656 , G06F2201/86
摘要： A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).
摘要翻译：提出了一种用于分布式片上调试触发的方法和装置。第一总线包括多条线路和可配置为监视第一总线的多条线路的调试状态机。一个或多个节点可配置为检测触发事件，并且响应于检测到一个或多个触发事件而使用分配给该节点的多条线路的第一子集向调试状态机提供信号。

4. 发明申请

US20140053036A1 DEBUGGING MULTIPLE EXCLUSIVE SEQUENCES USING DSM CONTEXT SWITCHES 审中-公开
标题翻译：使用DSM上下文开关调试多个独占序列
公开(公告)号：US20140053036A1
公开(公告)日：2014-02-20
申请号：US13586622
申请日：2012-08-15
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G01R31/3177
CPC分类号： G01R31/31705
摘要： A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (DSM). The DSM includes multiple programmable storage elements for storing parameter values corresponding to multiple contexts. Each context is associated with a given one of multiple instruction sequences, such as at least threads and power-performance states. The DSM detects a sequence identifier (ID) and selects a context based on the sequence ID. The corresponding parameter values are used by transition conditions (triggers) and taken debug actions in a finite state machine (FSM) within the DSM. Each state and transition in the FSM is used by each one of the multiple contexts. The programmable DSM shares many resources, rather than replicating them, while being used for multiple sequences.
摘要翻译：一种用于通过模内硬件高效调试集成电路的系统和方法。处理器核心包括片上调试状态机（DSM）。 DSM包括用于存储对应于多个上下文的参数值的多个可编程存储元件。每个上下文与多个指令序列中的给定的一个相关联，例如至少线程和功率性能状态。 DSM检测序列标识符（ID），并根据序列ID选择上下文。相应的参数值由转换条件（触发器）使用，并在DSM内的有限状态机（FSM）中采取调试动作。 FSM中的每个状态和转换由多个上下文中的每一个使用。可编程的DSM共享许多资源，而不是复制它们，而被用于多个序列。

5. 发明授权

US09129061B2 Method and apparatus for on-chip debugging 有权
标题翻译：用于片上调试的方法和装置
公开(公告)号：US09129061B2
公开(公告)日：2015-09-08
申请号：US13557756
申请日：2012-07-25
申请人： Scott P. Nixon , Tiger Lu , Eric M. Rentschler
发明人： Scott P. Nixon , Tiger Lu , Eric M. Rentschler
IPC分类号： G06F11/36
CPC分类号： G06F11/364 , G06F11/3648
摘要： The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.
摘要翻译：本发明提供一种用于动态配置调试触发模式的方法和装置。该方法的一个示例性实施例包括比较在总线的多条线路的第一子集上接收的比特值与第一比特模式，并响应于在总线的多条线路的第二子集上接收的比特值比较指示在第一子集上接收的比特的值与第一种比特模式相匹配。该方法的示例性实施例还包括使用捕获的值定义用于触发调试动作的第二模式。

6. 发明申请

US20140047262A1 MULTIPLE CLOCK DOMAIN TRACING 有权
标题翻译：多个时钟域追踪
公开(公告)号：US20140047262A1
公开(公告)日：2014-02-13
申请号：US13572249
申请日：2012-08-10
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F1/12
CPC分类号： G06F11/3656 , G06F1/10 , G06F1/14 , G06F11/3636
摘要： An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter fir counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.
摘要翻译：具有多个时钟域跟踪功能的集成电路包括一个调试模块，包括一个用于计数参考时钟信号的脉冲以提供全局时间戳的全局时间戳计数器，第一粒度计数器，用于对第一时钟信号的脉冲进行计数以提供第一粒度计数，第二粒度计数器计数第二时钟信号的脉冲以提供第二粒度计数，以及跟踪高速缓冲存储器，用于选择性地在第一分区中存储全局时间戳，第一粒度计数和与第一粒度同步的第一数据时钟信号，并且用于在第二分区中选择性地存储与第二时钟信号同步的全局时间戳，第二粒度计数和第二数据。

7. 发明申请

US20140053027A1 MULTIPLE CLOCK DOMAIN DEBUG CAPABILITY 有权
标题翻译：多个时钟域调试能力
公开(公告)号：US20140053027A1
公开(公告)日：2014-02-20
申请号：US13587631
申请日：2012-08-16
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/34
CPC分类号： G06F11/3656
摘要： An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.
摘要翻译：具有调试功能的集成电路包括：第一封隔器和同步器，用于组合从第一电路接收的第一触发信号的多个值以形成第一打包触发信号，并响应触发器输出同步的第一打包触发信号时钟信号，第一触发信号与第一源时钟信号同步;第一逻辑门，用于提供第一输出触发信号，指示第一同步打包触发信号中第一触发信号的第一多个数值是否为第一触发信号处于第一状态，并且调试状态机响应于第一输出触发信号选择性地提供第一动作信号。

8. 发明授权

US08832500B2 Multiple clock domain tracing 有权
标题翻译：多个时钟域跟踪
公开(公告)号：US08832500B2
公开(公告)日：2014-09-09
申请号：US13572249
申请日：2012-08-10
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656 , G06F1/10 , G06F1/14 , G06F11/3636
摘要： An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter for counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.
摘要翻译：具有多个时钟域跟踪功能的集成电路包括一个调试模块，包括一个用于计数参考时钟信号的脉冲以提供全局时间戳的全局时间戳计数器，第一粒度计数器，用于对第一时钟信号的脉冲进行计数以提供第一粒度计数，用于计数第二时钟信号的脉冲以提供第二粒度计数的第二粒度计数器和用于选择性地在第一分区中存储全局时间戳，第一粒度计数和与第一粒度同步的第一数据的跟踪高速缓冲存储器时钟信号，并且用于在第二分区中选择性地存储与第二时钟信号同步的全局时间戳，第二粒度计数和第二数据。

9. 发明申请

US20140122929A1 DISTRIBUTED ON-CHIP DEBUG TRIGGERING 有权
标题翻译：分布式片上调试触发
公开(公告)号：US20140122929A1
公开(公告)日：2014-05-01
申请号：US13665719
申请日：2012-10-31
申请人： Scott P. Nixon , Eric M. Rentschler
发明人： Scott P. Nixon , Eric M. Rentschler
IPC分类号： G06F11/273
CPC分类号： G06F11/27 , G06F11/3065 , G06F11/348 , G06F11/3648 , G06F11/3656 , G06F2201/86
摘要： A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).
摘要翻译：提出了一种用于分布式片上调试触发的方法和装置。第一总线包括多条线路和可配置为监视第一总线的多条线路的调试状态机。一个或多个节点可配置为检测触发事件，并且响应于检测到一个或多个触发事件而使用分配给该节点的多条线路的第一子集向调试状态机提供信号。

10. 发明申请

US20120144240A1 DEBUG STATE MACHINE AND PROCESSOR INCLUDING THE SAME 有权
标题翻译：调试状态机和处理器，包括它们
公开(公告)号：US20120144240A1
公开(公告)日：2012-06-07
申请号：US12958585
申请日：2010-12-02
申请人： Eric Rentschler , Steven J. Kommrusch , Scott P. Nixon
发明人： Eric Rentschler , Steven J. Kommrusch , Scott P. Nixon
IPC分类号： G06F11/07
CPC分类号： G06F11/3636
摘要： A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.
摘要翻译：公开了一种处理器或集成电路芯片，其包括调试状态机（DSM），其允许编程复杂的触发序列以实现灵活和有效的调试可见性。 DSM集中控制本地调试功能，如跟踪启动和停止，跟踪过滤，DSM之间的交叉触发，时钟停止，触发系统调试模式中断，灵活的微代码接口等。 DSM被配置为从处理器核心，其他DSM，北桥，其他插座等接收触发，并且在相应的触发或触发序列发生的条件下启动编程的动作。

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