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1. 发明授权

US06221769B1 Method for integrated circuit power and electrical connections via through-wafer interconnects 有权
标题翻译：用于通过晶片间互连的集成电路电源和电气连接的方法
公开(公告)号：US06221769B1
公开(公告)日：2001-04-24
申请号：US09263031
申请日：1999-03-05
申请人： Sang Hoo Dhong , Kevin John Nowka , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Kevin John Nowka , Michael Jay Shapiro
IPC分类号： H01L2144
CPC分类号： H01L21/486 , H01L21/76898 , H01L2224/16 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/15312 , H01L2924/00
摘要： A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.
摘要翻译：一种用于向集成电路硅封装提供贯穿晶片连接的方法。首先在硅封装中产生一个孔，其中内表面区域从硅封装的底表面延伸到硅封装的顶表面。孔由两种方法之一创建。第一个涉及以高速度旋转的钻石钻头的机械钻孔。第二个涉及使用浆料和钢指的超声波铣削。孔的内表面积被绝缘材料覆盖，以使稍后沉积的导电材料绝缘并用作扩散阻挡层，然后种子材料放置在孔中。最后，孔填充有导电材料，该导电材料用于提供大的功率输入或信号连接到集成电路芯片。

2. 发明授权

US6166437A Silicon on silicon package with precision align macro 有权
标题翻译：硅芯片封装，精确对准宏
公开(公告)号：US6166437A
公开(公告)日：2000-12-26
申请号：US290921
申请日：1999-04-12
申请人： Sang Hoo Dhong , Kevin John Nowka , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Kevin John Nowka , Michael Jay Shapiro
IPC分类号： H01L23/13 , H01L23/544 , H01L23/34 , H01L23/48 , H01L23/52
CPC分类号： H01L23/544 , H01L23/13 , H01L2223/54426 , H01L2224/10165 , H01L2224/81141 , H01L2924/00014 , H01L2924/15151 , H01L2224/0401
摘要： A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips. In the final stage of assembly, the package is restrained from movement and a pin is inserted through each hole in the wafer to force the chips into contact with the contacts on the package. Heat is then applied to fuse solder balls on the chips with the contacts to form a complete and finished assembly.
摘要翻译：蚀刻硅晶片以形成第一和第二系列的引导特征。第一系列的特征大于第二系列的特征并且围绕着第二系列的特征。第二个系列分组成群，在每组的中心形成一个孔。晶片被设计成将具有预成型触点的硅封装与多个硅基芯片集成。封装和每个芯片具有一系列引导凹槽，其分别对应于第一和第二系列的引导特征。一个芯片放置在第二个系列的每个组的顶部，并且包装被放置在第一系列的顶部。封装和芯片中的凹槽将精确地对准并滑动地接合特征的上端。由于第一系列的特征大于第二系列的特征，所以封装和芯片之间存在间隙。在组装的最后阶段，封装被限制移动，并且销穿过晶片中的每个孔，以迫使芯片与封装上的触点接触。然后施加热量以使具有触头的芯片上的焊球熔合以形成完整和完成的组件。

3. 发明授权

US06268660B1 Silicon packaging with through wafer interconnects 有权
标题翻译：通过晶圆互连的硅封装
公开(公告)号：US06268660B1
公开(公告)日：2001-07-31
申请号：US09263032
申请日：1999-03-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Michael Jay Shapiro
IPC分类号： H01L2348
CPC分类号： H01L23/5384 , H01L23/481 , H01L2224/16 , H01L2924/01322 , H01L2924/10253 , H01L2924/00
摘要： A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
摘要翻译：集成电路芯片封装。该封装包含具有顶表面和底表面的硅衬底。封装还包含用于将集成电路电连接到附接到衬底顶表面的衬底的第一装置。多层布线位于顶表面并且耦合到第一连接装置，并且用作多个第一连接装置之间的通信链路，以实现多芯片处理。用于将上表面的多层布线耦合到底表面的通孔容纳装置从底表面到顶表面穿过基底。还存在用于将基板的底表面处的耦合装置与外部部件连接的第二装置。

4. 发明授权

US08327126B2 Multicore processor and method of use that adapts core functions based on workload execution 有权
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08327126B2
公开(公告)日：2012-12-04
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/22 , G06F9/24 , G06F9/46
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

5. 发明授权

US08312455B2 Optimizing execution of single-threaded programs on a multiprocessor managed by compilation 有权
标题翻译：在编译器管理的多处理器上优化单线程程序的执行
公开(公告)号：US08312455B2
公开(公告)日：2012-11-13
申请号：US11960021
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译：一种用于优化多核处理器上单个线程程序的执行的方法。该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以供所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。

6. 发明申请

US20090164755A1 Optimizing Execution of Single-Threaded Programs on a Multiprocessor Managed by Compilation 有权
标题翻译：通过编译管理的多处理器上优化单线程程序的执行
公开(公告)号：US20090164755A1
公开(公告)日：2009-06-25
申请号：US11960021
申请日：2007-12-19
申请人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, JR. , Louis Bennie Capps, JR. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/312
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译：一种用于优化多核处理器上单个线程程序的执行的方法。该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以由所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。

7. 发明申请

US20080028236A1 Method and Apparatus for Controlling Heat Generation in a Multi-Core Processor 有权
标题翻译：用于控制多核处理器中的发热的方法和装置
公开(公告)号：US20080028236A1
公开(公告)日：2008-01-31
申请号：US11459988
申请日：2006-07-26
申请人： Louis Bennie Capps , Warren D. Dyckman , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/206
摘要： The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
摘要翻译：所公开的方法和装置可以减少多核处理器中的发热。在一个实施例中，多核处理器随着时间跨越处理器管芯以预定模式关闭所选择的处理器核，以减少处理器的平均发热量。所公开的多核处理器可以减少或避免影响处理器寿命的不期望的热点。

8. 发明授权

US08645673B2 Multicore processor and method of use that adapts core functions based on workload execution 失效
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08645673B2
公开(公告)日：2014-02-04
申请号：US13613936
申请日：2012-09-13
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/06 , G06F9/24
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

9. 发明授权

US08544006B2 Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict 有权
标题翻译：通过在发生冲突后由主要组件生成的寄存器和内存值重新启动失败的离散可执行子组件的执行来解决冲突
公开(公告)号：US08544006B2
公开(公告)日：2013-09-24
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

10. 发明申请

US20090094446A1 INTEGRATED CIRCUIT ENVIRONMENT INITIALIZATION ACCORDING TO INFORMATION STORED WITHIN THE INTEGRATED CIRCUIT 失效
标题翻译：集成电路环境初始化根据集成电路中存储的信息
公开(公告)号：US20090094446A1
公开(公告)日：2009-04-09
申请号：US12277365
申请日：2008-11-25
申请人： Louis Bennie Capps, JR. , Mark Elliott Hack , Steven Paul Hartman , Michael Jay Shapiro
发明人： Louis Bennie Capps, JR. , Mark Elliott Hack , Steven Paul Hartman , Michael Jay Shapiro
IPC分类号： G06F15/177
CPC分类号： G06F1/206
摘要： A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
摘要翻译：一种用于根据存储在集成电路的非易失性存储器中的信息自动初始化系统的操作设置的方法，使得当系统运行时系统满足可能是微处理器的集成电路的操作要求。在制造测试期间，集成电路的环境要求被确定并存储在集成电路的非易失性存储器内。在系统初始化期间，从集成电路读取的测试值确定所需的工作电压，频率和冷却要求等环境控制值。这些值由系统的接口从集成电路的接口读取。系统设置由值控制以提供所需的操作环境，并且可以在系统内捕获值以用于后续操作和初始化序列。

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