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1. 发明授权

US10950722B2 Vertical gate all-around transistor 有权
公开(公告)号：US10950722B2
公开(公告)日：2021-03-16
申请号：US14588337
申请日：2014-12-31
申请人： STMICROELECTRONICS, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John H. Zhang , Carl Radens , Lawrence A. Clevenger , Yiheng Xu
IPC分类号： H01L29/78 , H01L29/165 , H01L27/092 , H01L29/66 , H01L21/8238
摘要： Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

2. 发明授权

US09391020B2 Interconnect structure having large self-aligned vias 有权
标题翻译：互连结构具有大的自对准通孔
公开(公告)号：US09391020B2
公开(公告)日：2016-07-12
申请号：US14314945
申请日：2014-06-25
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Richard Stephen Wise , Akil K. Sutton , Terry Allen Spooner , Nicole A. Saulnier
IPC分类号： H01L23/48 , H01L23/522 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/76808 , H01L21/7681 , H01L21/76816 , H01L21/7682 , H01L21/76835 , H01L21/76843 , H01L21/76877 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
摘要翻译：公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

3. 发明授权

US09214429B2 Trench interconnect having reduced fringe capacitance 有权
标题翻译：具有降低的边缘电容的沟槽互连
公开(公告)号：US09214429B2
公开(公告)日：2015-12-15
申请号：US14098346
申请日：2013-12-05
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Hsueh-Chung Chen , Lawrence A. Clevenger , Yann Mignot , Carl Radens , Richard Stephen Wise , Yannick Loquet , Yiheng Xu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/7682 , H01L21/76831 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.
摘要翻译：在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

4. 发明申请

US20150162278A1 TRENCH INTERCONNECT HAVING REDUCED FRINGE CAPACITANCE 有权
标题翻译：具有减少的FRINGE电容的TRENCH INTERCONNECT
公开(公告)号：US20150162278A1
公开(公告)日：2015-06-11
申请号：US14098346
申请日：2013-12-05
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： John H. Zhang , Hsueh-Chung Chen , Lawrence A. Clevenger , Yann Mignot , Carl Radens , Richard Stephen Wise , Yannick Loquet , Yiheng Xu
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/7682 , H01L21/76831 , H01L21/76879 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.
摘要翻译：在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。

5. 发明授权

US08970004B2 Electrostatic discharge devices for integrated circuits 有权
标题翻译：用于集成电路的静电放电装置
公开(公告)号：US08970004B2
公开(公告)日：2015-03-03
申请号：US13725666
申请日：2012-12-21
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L29/00 , H01L27/02 , H01L21/266
CPC分类号： H01L27/0248 , H01L21/26586 , H01L21/266 , H01L27/0255
摘要： A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.
摘要翻译：公开了用于保护集成电路免受静电放电的结二极管阵列。结二极管集成了各种尺寸和功能的对称和非对称结二极管。一些结二极管被配置为通过未封装的互连线提供低电压和电流放电，而其它结构二极管被配置为通过封装的互连线提供高电压和电流放电。结二极管阵列元件包括p-n结二极管和N + / N + +结二极管。结二极管包括具有定制形状的植入区域。如果不需要对称和非对称二极管作为结二极管阵列的组件，则阵列配置有任一类型的二极管之间的隔离区域。一些结二极管阵列包括掩埋氧化物层，以防止掺杂剂扩散到超过选定深度的衬底中。

6. 发明申请

US20150002213A1 MODULAR FUSES AND ANTIFUSES FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的模块式熔断器和防爆装置
公开(公告)号：US20150002213A1
公开(公告)日：2015-01-01
申请号：US13931692
申请日：2013-06-28
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Edem Wornyo
IPC分类号： H01L23/525 , H01F17/02 , H01L49/02
CPC分类号： H01L23/5256 , H01F17/0006 , H01F17/02 , H01F2017/0073 , H01L23/522 , H01L23/5227 , H01L23/5252 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
摘要翻译：公开了纳米级电子元件，反熔丝和平面线圈电感器。铜镶嵌工艺可用于制造所有这些电路元件。可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。使用这种模块化阵列为集成电路设计人员提供了灵活性。

7. 发明申请

US20140183735A1 SYSTEM AND METHOD OF COMBINING DAMASCENES AND SUBTRACT METAL ETCH FOR ADVANCED BACK END OF LINE INTERCONNECTIONS 有权
标题翻译：用于线性互连的高级后端的组合金属离子和金属离子的组合的系统和方法
公开(公告)号：US20140183735A1
公开(公告)日：2014-07-03
申请号：US13731878
申请日：2012-12-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , STMICROELECTRONICS, INC.
发明人： John H. ZHANG , Lawrence A. Clevenger , Carl Radens , Yiheng XU , Walter Kleemeier , Cindy Goldberg
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L23/5384 , H01L21/76807 , H01L21/7682 , H01L21/76883 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
摘要翻译：金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。在电介质层中形成宽沟槽。导电材料沉积在宽沟槽中。在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

8. 发明授权

US10319630B2 Encapsulated damascene interconnect structure for integrated circuits 有权
公开(公告)号：US10319630B2
公开(公告)日：2019-06-11
申请号：US13629411
申请日：2012-09-27
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L23/48 , H01L23/52 , H01L21/768 , H01L23/522 , H01L23/532
摘要： A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

9. 发明申请

US20180144926A1 ADVANCED INTERCONNECT WITH AIR GAP 审中-公开
公开(公告)号：US20180144926A1
公开(公告)日：2018-05-24
申请号：US15874654
申请日：2018-01-18
申请人： STMicroelectronics, Inc. , International Business Machines Corporation
发明人： John H. Zhang , Yann Mignot , Lawrence A. Clevenger , Carl Radens , Richard Stephen Wise , Yiheng Xu , Yannick Loquet , Hsueh-Chung Chen
IPC分类号： H01L21/02 , H01L21/768 , H01L21/311 , H01L23/522 , H01L23/532
CPC分类号： H01L21/0217 , H01L21/31144 , H01L21/7682 , H01L21/76831 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

10. 发明申请

US20160218070A1 MULTILAYER STRUCTURE IN AN INTEGRATED CIRCUIT FOR DAMAGE PREVENTION AND DETECTION AND METHODS OF CREATING THE SAME 有权
标题翻译：用于损坏预防和检测的集成电路中的多层结构及其创建方法
公开(公告)号：US20160218070A1
公开(公告)日：2016-07-28
申请号：US15090996
申请日：2016-04-05
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Byoung Youp Kim , Walter Kleemeier
IPC分类号： H01L23/00 , H01L21/66 , H01L23/532 , H01L21/768 , H01L23/528
CPC分类号： H01L23/562 , H01L21/76805 , H01L21/76843 , H01L21/76897 , H01L22/12 , H01L22/14 , H01L22/32 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/528 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.
摘要翻译：各种实施例便于集成电路的管芯保护。在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

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