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1. 发明申请

WO2020139423A1 MULTI-PASS PROGRAMMING PROCESS FOR MEMORY DEVICE WHICH OMITS VERIFY TEST IN FIRST PROGRAM PASS 审中-公开
公开(公告)号：WO2020139423A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/047988
申请日：2019-08-23
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , LU, Ching-Huang , DIEP, Vinh , DONG, Yingda
IPC分类号： G11C16/08 , G11C16/10 , G11C16/04 , G11C11/56 , G11C16/34
摘要： Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

2. 发明申请

WO2020131168A1 REDUCING READ DISTURB IN TWO-TIER MEMORY DEVICE BY MODIFYING DURATION OF CHANNEL DISCHARGE BASED ON SELECTED WORD LINE 审中-公开
公开(公告)号：WO2020131168A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/047975
申请日：2019-08-23
申请人： SANDISK TECHNOLOGIES LLC
发明人： CHEN, Hong-Yan , ZHAO, Wei , DONG, Yingda
IPC分类号： G11C16/26 , G11C16/08 , G11C16/04 , H01L27/11556
摘要： Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.

3. 发明申请

WO2020005332A1 THREE-DIMENSIONAL INVERSE FLAT NAND MEMORY DEVICE CONTAINING PARTIALLY DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF MAKING THE SAME 审中-公开
公开(公告)号：WO2020005332A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/018621
申请日：2019-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHOU, Fei , DONG, Yingda , MAKALA, Raghuveer S.
IPC分类号： H01L27/11551 , H01L27/11578 , H01L27/11524
摘要： A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail. Each memory stack structure includes a vertical semiconductor channel, a blocking dielectric contacting an outer sidewall of the vertical semiconductor channel, and a charge storage layer contacting an outer sidewall of the blocking dielectric, vertically extending continuously through each level of the electrically conductive strips, and having a vertically undulating lateral thickness.

4. 发明申请

WO2019099105A1 REDUCING PROGRAM DISTURB BY MODIFYING WORD LINE VOLTAGES AT INTERFACE IN TWO-TIER STACK AFTER PROGRAM-VERIFY 审中-公开
公开(公告)号：WO2019099105A1
公开(公告)日：2019-05-23
申请号：PCT/US2018/052366
申请日：2018-09-24
申请人： SANDISK TECHNOLOGIES LLC
发明人： CHEN, Hong-Yan , DONG, Yingda
IPC分类号： G11C16/34 , G11C16/04 , G11C16/10 , H01L27/1157
摘要： A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells are decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.

5. 发明申请

WO2018231299A1 REDUCING SELECT GATE INJECTION DISTURB AT THE BEGINNING OF AN ERASE OPERATION 审中-公开
公开(公告)号：WO2018231299A1
公开(公告)日：2018-12-20
申请号：PCT/US2018/021277
申请日：2018-03-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： DIEP, Vinh , YU, Xuehong , ZHANG, Zhengyi , DONG, Yingda
IPC分类号： G11C11/56 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/34 , G11C16/14 , G11C16/04
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C2216/28
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.

6. 发明申请

WO2018048490A1 BLOCK HEALTH MONITORING USING THRESHOLD VOLTAGE OF DUMMY MEMORY CELLS 审中-公开
标题翻译：基于虚电内存阈值电压的健康监测
公开(公告)号：WO2018048490A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/034891
申请日：2017-05-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： PANG, Liang , YU, Xuehong , DONG, Yingda , YANG, Nian Niles
IPC分类号： G11C16/34 , G11C7/14 , G11C16/04 , G11C11/56
摘要： Techniques are provided for measuring the endurance of a set of data memory cells by evaluating the threshold voltage (Vth) of associated dummy memory cells. A cell has a high endurance or good data retention if it is able to maintain the charges. However, there can be a variation in the endurance of cells even within a single die. By evaluating the dummy memory cells, an early warning can be obtained of a degradation of the data memory cells. Moreover, there is no interference with the operation of the data memory cells. Based on a number of dummy memory cells which have a Vth below a demarcation voltage, a corrective action is taken such as adjusting read voltages, an initial program voltage and/or an initial erase voltage, or marking the block as being bad and recovering the data.
摘要翻译：通过评估关联的虚存储单元的阈值电压（Vth）来提供用于测量一组数据存储单元的耐久性的技术。如果电池能够维持充电，则电池具有高耐久性或良好的数据保留。但是，即使在一个模具内，电池的耐久性也可能有所不同。通过评估伪存储单元，可以获得数据存储单元退化的预警。而且，不会干扰数据存储单元的操作。基于具有低于分界电压Vth的虚拟存储器单元的数量，采取诸如调整读取电压，初始编程电压和/或初始擦除电压的校正动作，或者将块标记为坏并且恢复数据

7. 发明申请

WO2018022184A1 NON-VOLATILE MEMORY WITH REDUCED PROGRAM SPEED VARIATION 审中-公开
标题翻译：非易失性存储器，程序速度变化较小
公开(公告)号：WO2018022184A1
公开(公告)日：2018-02-01
申请号：PCT/US2017/034888
申请日：2017-05-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARASKAR, Ashish , PANG, Liang , ZHANG, Yanli , MAKALA, Raghuveer , DONG, Yingda
IPC分类号： H01L27/11556 , H01L27/11582 , H01L29/788 , H01L29/792
摘要： A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.
摘要翻译：三维非易失性存储器具有跨越字线的减少的编程变化。字线的栅极长度从记忆孔的顶部到底部逐渐减小。由于存储空间狭窄，编程速度的提高被相应位置的较小栅极长度所抵消。阻挡电介质厚度也可以独立地或与可变字线厚度结合地变化。阻挡电介质形成有水平厚度，该水平厚度在与下字线层相邻的区域处更大并且在与上字线层相邻的区域处更小。较低字线层的较大厚度降低了较低字线相对于较高字线的存储空间中的编程速度。由于记忆孔直径的差异导致的编程速度的变化可能被阻挡电介质厚度的相应变化所抵消。

8. 发明申请

WO2019139670A1 THREE-DIMENSIONAL MEMORY DEVICE INCLUDING PARTIALLY SURROUNDING SELECT GATES AND FRINGE FIELD ASSISTED PROGRAMMING THEREOF 审中-公开
公开(公告)号：WO2019139670A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/060847
申请日：2018-11-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： ZHANG, Yanli , ZHANG, Peng , ALSMEIER, Johann , DONG, Yingda
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157
摘要： A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.

9. 发明申请

WO2019070429A1 REDUCING DISTURBS WITH DELAYED RAMP UP OF DUMMY WORD LINE AFTER PRE-CHARGE DURING PROGRAMMING 审中-公开
公开(公告)号：WO2019070429A1
公开(公告)日：2019-04-11
申请号：PCT/US2018/052331
申请日：2018-09-23
申请人： SANDISK TECHNOLOGIES LLC
发明人： YU, Xuehong , DONG, Yingda
IPC分类号： G11C16/32 , G11C16/34 , G11C16/08 , G11C16/04 , H01L27/11529
摘要： A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.

10. 发明申请

WO2019022810A1 NON-VOLATILE MEMORY WITH METHODS TO REDUCE CREEP-UP FIELD BETWEEN DUMMY CONTROL GATE AND SELECT GATE 审中-公开
公开(公告)号：WO2019022810A1
公开(公告)日：2019-01-31
申请号：PCT/US2018/032439
申请日：2018-05-11
申请人： SANDISK TECHNOLOGIES LLC
发明人： LU, Ching-Huang , KHANDELWAL, Anubhav , CHEN, Changyuan , HSU, Cynthia , DONG, Yingda
IPC分类号： G11C16/04 , G11C16/26 , G11C16/34
摘要： Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

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