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1. 发明专利

SG10201905158TA SEMICONDUCTOR PACKAGE 未知
公开(公告)号：SG10201905158TA
公开(公告)日：2020-02-27
申请号：SG10201905158T
申请日：2019-06-06
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HEE-JEONG KIM , JUHYUN LYU , UN-BYOUNG KANG , JONGHO LEE
摘要： Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first thermal interface material segment between the first and second semiconductor structures and a second thermal interface material segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of of the first thermal interface material segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second thermal interface material segment.

2. 发明公开

US20240162193A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20240162193A1
公开(公告)日：2024-05-16
申请号：US18213852
申请日：2023-06-25
申请人： Samsung Electronics Co., Ltd.
发明人： Seongyo KIM , UN-BYOUNG KANG , SANG-SICK PARK , Hanmin LEE , Seungyoon JUNG
IPC分类号： H01L25/065 , B23K26/38 , B23K26/40 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/48
CPC分类号： H01L25/0657 , B23K26/38 , B23K26/40 , H01L21/565 , H01L23/3128 , H01L23/481 , H01L24/16 , H01L24/32 , H01L24/73 , B23K2101/40 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/06517 , H01L2225/06541
摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. The lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. The upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.

3. 发明公开

US20230230946A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20230230946A1
公开(公告)日：2023-07-20
申请号：US17939127
申请日：2022-09-07
申请人： Samsung Electronics Co., Ltd.
发明人： Seongyo KIM , UN-BYOUNG KANG , MINSOO KIM , SANG-SICK PARK , Seungyoon JUNG
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/09 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/08 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/81203 , H01L24/81 , H01L2924/3511 , H01L2924/182 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06544 , H01L2225/06589 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/1703 , H01L2224/17055 , H01L2224/17104 , H01L2224/17179 , H01L2224/17132 , H01L2224/16012 , H01L2224/16055 , H01L2224/16059 , H01L2224/16104 , H01L2224/0801 , H01L2224/08056 , H01L2224/08055 , H01L2224/0903 , H01L2224/09179 , H01L2224/09132 , H01L2224/73204
摘要： A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

4. 发明申请

US20210125955A1 STACKED SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20210125955A1
公开(公告)日：2021-04-29
申请号：US16992895
申请日：2020-08-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JIHWAN SUH , UN-BYOUNG KANG , TAEHUN KIM , HYUEKJAE LEE , JIHWAN HWANG , SANG CHEON PARK
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18
摘要： A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

5. 发明公开

US20240120251A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20240120251A1
公开(公告)日：2024-04-11
申请号：US18213851
申请日：2023-06-25
申请人： Samsung Electronics Co., Ltd.
发明人： JIN-WOO PARK , UN-BYOUNG KANG , CHUNGSUN LEE
IPC分类号： H01L23/31 , H01L21/56 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L23/3157 , H01L21/56 , H01L24/08 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/08145 , H01L2224/16145 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/81203 , H01L2224/92125 , H10B80/00
摘要： Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base semiconductor chip, a chip structure on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a molding layer surrounding the chip structure and the connection terminal. The chip structure includes a first semiconductor chip including a first frontside pad and a first backside pad, and a second semiconductor including a second frontside pad and a second backside pad. A lateral surface of the first semiconductor chip is aligned with that of the second semiconductor chip. The first backside pad and the second frontside pad partially overlap each other when viewed in plan while being in direct contact with each other. The first backside pad and the second frontside pad include the same metal and are formed into a single unitary piece.

6. 发明公开

US20230275052A1 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME 审中-公开
公开(公告)号：US20230275052A1
公开(公告)日：2023-08-31
申请号：US18313560
申请日：2023-05-08
申请人： Samsung Electronics Co., Ltd.
发明人： JU-IL CHOI , UN-BYOUNG KANG , JIN HO AN , JONGHO LEE , JEONGGI JIN , ATSUSHI FUJISAKI
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/11 , H01L24/13 , H01L24/03 , H01L2224/13113 , H01L2224/03614 , H01L2224/0346 , H01L2224/0401 , H01L2224/05016 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05144 , H01L2224/11849 , H01L2224/13026 , H01L2224/13111 , H01L2224/13116 , H01L2224/13155 , H01L2224/13144 , H01L2224/13139 , H01L2224/13147
摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

7. 发明申请

US20230111854A1 SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20230111854A1
公开(公告)日：2023-04-13
申请号：US17851245
申请日：2022-06-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： JU-IL CHOI , UN-BYOUNG KANG , MINSEUNG YOON , YONGHOE CHO , JEONGGI JIN , YUN SEOK CHOI
IPC分类号： H01L25/10 , H01L23/538 , H01L23/498 , H01L23/31 , H01L23/00 , H01L23/48
摘要： Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

8. 发明申请

US20220028834A1 SEMICONDUCTOR PACKAGE 有权
公开(公告)号：US20220028834A1
公开(公告)日：2022-01-27
申请号：US17245913
申请日：2021-04-30
申请人： Samsung Electronics Co., Ltd.
发明人： HYUEKJAE LEE , UN-BYOUNG KANG , SANG CHEON PARK , JINKYEONG SEOL , SANGHOON LEE
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00 , H01L25/00
摘要： A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

9. 发明申请

US20170125387A1 CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170125387A1
公开(公告)日：2017-05-04
申请号：US15402521
申请日：2017-01-10
申请人： Samsung Electronics Co., Ltd.
发明人： UN-BYOUNG KANG , Tae-Je Cho , Byung-Hyug Roh
IPC分类号： H01L25/065 , H01L21/56 , H01L23/31 , H01L21/78 , H01L23/00 , H01L25/00 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L23/295 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2224/0231 , H01L2224/02372 , H01L2224/0346 , H01L2224/0401 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06131 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/1413 , H01L2224/14181 , H01L2224/16113 , H01L2224/16146 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/1713 , H01L2224/17181 , H01L2224/73204 , H01L2224/9202 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2924/05442 , H01L2924/0665 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/186 , H01L2924/00 , H01L2224/81 , H01L2924/00014 , H01L2224/11 , H01L2924/014
摘要： A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

10. 发明公开

US20240204026A1 IMAGE SENSOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20240204026A1
公开(公告)日：2024-06-20
申请号：US18223307
申请日：2023-07-18
申请人： Samsung Electronics Co., Ltd.
发明人： JUNGHOON KANG , UN-BYOUNG KANG , SEUNGWAN SHIN , JUNG HYUN LEE
IPC分类号： H01L27/146
CPC分类号： H01L27/14634 , H01L27/14618 , H01L27/14623 , H01L27/14636
摘要： An image sensor package according to an embodiment includes: a substrate including a metal portion; an image sensor chip on the substrate; and a transparent glass cover disposed on the substrate and including an upper plate and sidewalls, the upper plate and the sidewalls defined by a cavity at a lower portion and spaced from the image sensor chip, wherein the sidewalls are directly bonded to the metal portion of the substrate, and the image sensor chip is sealed by the transparent glass cover and the substrate.

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