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1. 发明申请

US20140269057A1 NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD 有权
标题翻译：非易失性存储器件和编程方法
公开(公告)号：US20140269057A1
公开(公告)日：2014-09-18
申请号：US14211077
申请日：2014-03-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YOAV SHERESHEVSKI , AVNER DOR , SHMUEL DASHEVSKY , JUN JIN KONG , PIL SANG YOON
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3459
摘要： A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage.
摘要翻译：非易失性存储器件的编程方法包括：定义一组验证电压，将小于或等于第一目标编程电压的验证电压之间的最大验证电压设置为目标验证电压，基于目标验证电压和第一目标计算额外脉冲数编程电压，通过向存储单元施加增量步进脉冲程序（ISPP）脉冲，然后在验证集合中施加至少一个验证电压来验证存储器单元的阈值电压是否等于或大于目标验证电压并且当阈值电压被验证为等于或大于目标验证电压时，进一步将ISPP脉冲施加到存储器单元等于额外脉冲数的次数。

2. 发明申请

US20190050343A1 NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME 审中-公开
公开(公告)号：US20190050343A1
公开(公告)日：2019-02-14
申请号：US15671855
申请日：2017-08-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： ELONA EREZ , AVNER DOR , JUN-JIN KONG
IPC分类号： G06F12/1009 , G06F3/06
摘要： A method of controlling a nonvolatile memory device includes: receiving a plurality of logical pages associated with a plurality of physical addresses, respectively; storing the plurality of logical pages at the plurality of physical addresses in a selected one of a plurality of sub-clusters according to a given order of logical addresses of the logical pages; generating a first table including an entry for each one of the ordered logical addresses identifying a cluster of the selected sub-cluster and an offset into the selected sub-cluster; and generating a second table including an entry for the selected sub-cluster and the cluster indicating one of the ordered logical addresses associated with a first physical page of the selected sub-cluster.

3. 发明申请

US20170160978A1 FLASH MEMORY DEVICE INCLUDING DEDUPLICATION, AND RELATED METHODS 有权
公开(公告)号：US20170160978A1
公开(公告)日：2017-06-08
申请号：US14956715
申请日：2015-12-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： ELONA EREZ , AVNER DOR , JUN JIN KONG
IPC分类号： G06F3/06
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0679 , G06F12/00 , G11C7/1006 , G11C16/0483 , G11C16/10
摘要： A flash memory device includes physical pages that store data sectors therein. The method of operating the flash memory device includes receiving write data sectors to be stored in the flash memory device, pairing the write data sectors with write data sectors and with written data sectors previously stored in physical pages of the flash memory device based upon a matching and deduplication operation to define data sector pairs and a difference therebetween, and rewriting to the physical pages of the flash memory device, in a partial-page writing mode, to store the difference between the write data sector and its respective paired data sector. The partial-page writing mode is performed on a respective physical page after a previous programming and before erasing. The written data sectors included in the data sector pairs only partially occupy the corresponding physical page of the flash memory device. The difference between the write data sector and its respective paired data sector is stored in an unoccupied portion of the corresponding physical page of the flash memory device.

4. 发明申请

US20170149451A1 METHOD OF SIMILARITY TESTING BY SYNDROMES AND APPARATUS THEREFORE 有权
公开(公告)号：US20170149451A1
公开(公告)日：2017-05-25
申请号：US14949458
申请日：2015-11-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YARON SHANY , AVNER DOR , ELONA EREZ , JUN JIN KONG
IPC分类号： H03M13/15 , H03M13/19 , H03M13/00
CPC分类号： G06F3/0641 , G06F3/0608 , G06F11/1453 , G06F17/30156 , H03M13/136 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/1575 , H03M13/19 , H03M13/611
摘要： A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.

5. 发明申请

US20210376859A1 LOW POWER ECC FOR EUFS 有权
公开(公告)号：US20210376859A1
公开(公告)日：2021-12-02
申请号：US16885772
申请日：2020-05-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： AVNER DOR , Amit Berman , Ariel Doubchak
IPC分类号： H03M13/13 , H03M13/11 , H03M13/29 , G06F7/544
摘要： Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

6. 发明申请

US20170161202A1 FLASH MEMORY DEVICE INCLUDING ADDRESS MAPPING FOR DEDUPLICATION, AND RELATED METHODS 审中-公开
公开(公告)号：US20170161202A1
公开(公告)日：2017-06-08
申请号：US14957114
申请日：2015-12-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： ELONA EREZ , AVNER DOR , JUN JIN KONG
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F3/06 , G06F12/0246 , G06F2212/1024 , G06F2212/2022 , G06F2212/7201 , G06F2212/7205 , G06F2212/7207
摘要： A data storage device includes a flash memory that includes blocks of physical pages that include physical sectors configured to store data therein. A memory control unit, including a flash translation layer (FTL), is configured to receive write data sectors to be stored in the flash memory, determine at least one matched data sector by matching a write data sector with a reference data sector based upon a deduplication operation, and store the reference data sector corresponding to the matched data sector in a physical sector of a physical page of a block in the flash memory. Logical-to-physical addresses of the reference data sector and the corresponding matched data sector are mapped in the FTL, and physical-to-logical information regarding the corresponding matched data sector is written in a designated physical-to-logical information area of the flash memory. The physical-to-logical information area may be a metadata area of a physical sector, an adjacent physical sector in a same page, a last sector of a block or a dedicated block of the flash memory.

7. 发明申请

US20140281827A1 MEMORY CONTROLLER, METHOD OF OPERATING THE SAME, AND SYSTEM INCLUDING THE SAME 有权
标题翻译：存储器控制器，其操作方法和包括其的系统
公开(公告)号：US20140281827A1
公开(公告)日：2014-09-18
申请号：US14208340
申请日：2014-03-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： MOSHE TWITTO , AVNER DOR , JUN JIN KONG , Chang Kyu SEOl , HONG RAK SON
IPC分类号： G06F11/10
CPC分类号： G06F11/1072 , G06F11/108
摘要： A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.
摘要翻译：使用存储器控制器处理数据的方法包括基于每个多级单元的当前单元状态来确定可以改变多个多电平单元中的每一个的至少一个单元状态，其中每个多电平单元包括多个数据页; 当数据页的值基于映射到所述至少一个单元状态的映射值具有单个映射值并且生成关于所述卡位的卡位位数据时，将所述数据页之一确定为具有卡住位; 以及基于所述卡住的位数据对要存储在所述多级单元中的写入数据进行编码。

8. 发明申请

US20190114228A1 BOSE-CHAUDHURI-HOCQUENCHEM (BCH) ENCODING AND DECODING TAILORED FOR REDUNDANT ARRAY OF INEXPENSIVE DISKS (RAID) 审中-公开
公开(公告)号：US20190114228A1
公开(公告)日：2019-04-18
申请号：US15730943
申请日：2017-10-12
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： MOSHE TWITTO , YARON SHANY , AVNER DOR , ELONA EREZ , JUN JIN KONG
IPC分类号： G06F11/10 , G06F3/06 , H03M13/15 , H03M13/29
CPC分类号： G06F11/1076 , G06F3/0619 , G06F11/1072 , H03M13/1515 , H03M13/152 , H03M13/29 , H03M13/2906
摘要： A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n−{tilde over (k)}j, where the first n−kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n−{tilde over (k)}j)(n−{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n−kl columns and Tj has k1−{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n−{tilde over (k)}j; and solving ( A | I )  ( a b ) = ( Q j | T j )  s ~ = T j  s where a=0 and b=Tjs, and codeword c is nonzero only on the last n−{tilde over (k)}j=n−kj bits.

9. 发明申请

US20220021401A1 LOW-POWER ERROR CORRECTION CODE COMPUTATION IN GF (2R) 有权
公开(公告)号：US20220021401A1
公开(公告)日：2022-01-20
申请号：US16929983
申请日：2020-07-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： AVNER DOR , Amit Berman , Ariel Doubchak , Elik Almog Sheffi , Yaron Shany
IPC分类号： H03M13/15 , H03M13/00
摘要： A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2r) is a Galois field of 2r elements, ω=Σ0≤i≤r−1βi×αi wherein α is a fixed primitive element of F, and βi∈GF(2), wherein K=GF(2s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω1+α×ω2, ω1=Σ0≤i≤s−1γi×δi∈K, ω2=Σ0≤i≤s−1γi+s×δi∈K, and γ=[γ0, . . . , γr−1]T∈GF(2)r; accessing a first table with ω1 to obtain ω3=ω1−1, computing ω2×ω3 in field K, accessing a second table with ω2=ω3 to obtain (1+α×ω2×ω3)−1=ω4+α×ω5, wherein ω−1=(ω1×(1+α×ω2×ω3))−1=ω3×(ω4+α×ω5)=ω3×ω4+α×ω3×ω5; and computing products ω3×ω4 and ω3×ω5 to obtain ω−1=Σ0≤i≤s−1θi×δi+α·Σi≤i≤s−1θi+s=δi where θi∈GF(2).

10. 发明申请

US20190007062A1 EFFICIENT GENERALIZED TENSOR PRODUCT CODES ENCODING SCHEMES 审中-公开
公开(公告)号：US20190007062A1
公开(公告)日：2019-01-03
申请号：US15639475
申请日：2017-06-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： MOSHE TWITTO , MOSHE BEN ARI , AVNER DOR , ELONA EREZ , JUN JIN KONG , YARON SHANY
IPC分类号： H03M13/15 , H03M13/29 , H03M13/00
CPC分类号： H03M13/152 , H03M13/1515 , H03M13/2906 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/356 , H03M13/3707 , H03M13/616 , H03M13/617
摘要： A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises Δt syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying s by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=Ũ·s.

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