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1. 发明申请

WO2019212971A1 PERSISTENT WRITE DATA FOR ENERGY-BACKED MEMORY 审中-公开
公开(公告)号：WO2019212971A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/029657
申请日：2019-04-29
申请人： QUALCOMM INCORPORATED
发明人： BAINS, Kuljit Singh , RAMANUJAN, Raj , WANG, Liyong , QUEEN, Wesley
IPC分类号： G06F12/02
摘要： In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.

2. 发明申请

WO2019055164A1 PERSISTENT WRITES FOR NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2019055164A1
公开(公告)日：2019-03-21
申请号：PCT/US2018/046590
申请日：2018-08-14
申请人： QUALCOMM INCORPORATED
发明人： RAMANUJAN, Raj , BAINS, Kuljit Singh , WANG, Liyong , QUEEN, Wesley
IPC分类号： G06F12/02
摘要： Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.

3. 发明申请

WO2017209921A1 PERIODIC ZQ CALIBRATION WITH TRAFFIC-BASED SELF-REFRESH IN A MULTI-RANK DDR SYSTEM 审中-公开
标题翻译：基于流量的自刷新多周期DDR系统的定期ZQ校准
公开(公告)号：WO2017209921A1
公开(公告)日：2017-12-07
申请号：PCT/US2017/032421
申请日：2017-05-12
申请人： QUALCOMM INCORPORATED
发明人： WANG, Liyong
IPC分类号： G11C7/10 , G11C29/02 , G11C29/12 , G11C11/406 , G11C11/4093 , G11C29/50 , G06F13/16 , H04L25/02 , G11C29/44
摘要： According to various aspects, a memory controller may schedule ZQ commands to periodically calibrate individual memory ranks in a multi-rank memory. The memory controller may schedule a ZQ short command at each ZQ interval and record that the ZQ short command was missed with respect to a memory rank in a self-refresh mode at the ZQ interval. After the missed ZQ short commands reaches a first threshold, a ZQ long command may be scheduled at the next ZQ interval and normal ZQ behavior may resume in the event that the memory rank exits the self-refresh mode and the ZQ long command is executed. However, if the memory rank stays in the self-refresh mode until missed ZQ long commands reaches a second threshold, the memory controller may trigger a ZQ long command once the memory rank exits the self-refresh mode and skip a next ZQ calibration before resuming normal ZQ behavior.
摘要翻译：根据各个方面，存储器控制器可以调度ZQ命令以周期性地校准多秩存储器中的各个存储器等级。存储器控制器可以在每个ZQ间隔处调度ZQ短命令，并记录ZQ短命令相对于在ZQ间隔处的自刷新模式下的存储器等级。在错过的ZQ短命令达到第一阈值之后，可以在下一个ZQ间隔处调度ZQ长命令，并且在存储器秩退出自刷新模式和执行ZQ长命令的情况下可以恢复正常ZQ行为。然而，如果存储器列保持自刷新模式直到错过的ZQ长命令达到第二阈值，则存储器控制器可在存储器列退出自刷新模式后触发ZQ长命令，并在恢复之前跳过下一个ZQ校准正常的ZQ行为。

4. 发明申请

WO2019089683A1 WRITE CREDITS MANAGEMENT FOR NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2019089683A1
公开(公告)日：2019-05-09
申请号：PCT/US2018/058343
申请日：2018-10-31
申请人： QUALCOMM INCORPORATED
发明人： BAINS, Kuljit Singh , RAMANUJAN, Raj , QUEEN, Wesley , WANG, Liyong
IPC分类号： G06F13/16
摘要： Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.

5. 发明申请

WO2018102538A1 PROVIDING EXTENDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) BURST LENGTHS IN PROCESSOR-BASED SYSTEMS 审中-公开
公开(公告)号：WO2018102538A1
公开(公告)日：2018-06-07
申请号：PCT/US2017/063921
申请日：2017-11-30
申请人： QUALCOMM INCORPORATED
发明人： BAINS, Kuljit, Singh , QUEEN, Wesley , WANG, Liyong
IPC分类号： G06F13/16 , G06F13/28
摘要： Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems is disclosed. In one aspect, a processor-based system includes a DRAM circuit (e.g., disposed on a common x4/x8 die) providing 4-bit-wide data access ("x4") and a 128-bit internal data prefetch. When operated in a x4 mode, the DRAM circuit is configured to provide an extended DRAM burst length of 32 bits ("BL32"). The DRAM circuit receives a memory read request from a memory controller communicatively coupled to the DRAM circuit, prefetches 128 bits of data, and returns all of the 128 bits of fetched data to the memory controller in response to the memory read request. In some aspects, the DRAM circuit may also receive a memory write command including 128 bits of write data from the memory controller, and write the 128 bits of write data to memory without performing a read/modify/write (RMW) operation.

6. 发明申请

WO2018156780A1 PROVIDING SINGLE DATA RATE (SDR) MODE OR DOUBLE DATA RATE (DDR) MODE FOR THE COMMAND AND ADDRESS (CA) BUS OF REGISTERING CLOCK DRIVE (RCD) FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) 审中-公开
公开(公告)号：WO2018156780A1
公开(公告)日：2018-08-30
申请号：PCT/US2018/019251
申请日：2018-02-22
申请人： QUALCOMM INCORPORATED
发明人： WANG, Liyong , BAINS, Kuljit Singh , QUEEN, Wesley
IPC分类号： G06F13/16
摘要： Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.

7. 发明申请

WO2014110050A1 MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS 审中-公开
标题翻译：具有适应性开放数量的存储设备
公开(公告)号：WO2014110050A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010544
申请日：2014-01-07
申请人： QUALCOMM INCORPORATED
发明人： SHEN, Jian , WANG, Liyong , CHUA-EOAN, Lew
IPC分类号： G11C7/10 , G11C11/408 , G11C11/4093
CPC分类号： G11C8/18 , G06F3/0604 , G06F3/0638 , G06F3/0653 , G06F3/0673 , G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/10 , G06F13/1689 , G06F2212/1016 , G06F2212/60 , G11C7/1039 , G11C8/06 , G11C8/10 , G11C11/4082 , G11C11/4093
摘要： A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.
摘要翻译：存储器件包括存储器阵列，至少一个行地址缓冲器，一组行数据缓冲器，行解码器，读出放大器阵列和解复用器。存储器阵列包括组织成行和列的数据元素。每行都可以通过行地址寻址。每行中的每个数据元素都可以通过列地址进行寻址。至少一个行地址缓冲器保存一组连续选择的行地址的所选行地址。行数据缓冲器集合保持与所选择的一组连续的行地址对应的所选行的各个内容。行解码器解码所选择的行地址以访问所选行。读出放大器的阵列通过解复用器读取所选择的行并将所选行的内容发送到行数据缓冲器中的一个，并将所选行的内容写回所选行。

8. 发明公开

EP3704591A1 WRITE CREDITS MANAGEMENT FOR NON-VOLATILE MEMORY 有权
公开(公告)号：EP3704591A1
公开(公告)日：2020-09-09
申请号：EP18804191.7
申请日：2018-10-31
申请人： Qualcomm Incorporated
发明人： BAINS, Kuljit Singh , RAMANUJAN, Raj , QUEEN, Wesley , WANG, Liyong
IPC分类号： G06F13/16

9. 发明公开

EP3788491A1 PERSISTENT WRITE DATA FOR ENERGY-BACKED MEMORY 审中-公开
公开(公告)号：EP3788491A1
公开(公告)日：2021-03-10
申请号：EP19722996.6
申请日：2019-04-29
申请人： QUALCOMM INCORPORATED
发明人： BAINS, Kuljit Singh , RAMANUJAN, Raj , WANG, Liyong , QUEEN, Wesley
IPC分类号： G06F12/02

10. 发明授权

EP2943956B1 MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS 失效
公开(公告)号：EP2943956B1
公开(公告)日：2018-10-03
申请号：EP14702117.4
申请日：2014-01-07
申请人： Qualcomm Incorporated
发明人： SHEN, Jian , WANG, Liyong , CHUA-EOAN, Lew
IPC分类号： G11C7/10 , G11C11/408 , G11C11/4093
CPC分类号： G11C8/18 , G06F3/0604 , G06F3/0638 , G06F3/0653 , G06F3/0673 , G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/10 , G06F13/1689 , G06F2212/1016 , G06F2212/60 , G11C7/1039 , G11C8/06 , G11C8/10 , G11C11/4082 , G11C11/4093
摘要： A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

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