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1. 发明授权

US06804165B2 Latency time switch for an S-DRAM 失效
标题翻译： S-DRAM的延迟时间切换
公开(公告)号：US06804165B2
公开(公告)日：2004-10-12
申请号：US10374657
申请日：2003-02-26
申请人： Peter Schrögmeier , Stefan Dietrich , Sabine Kieser , Pramod Acharya
发明人： Peter Schrögmeier , Stefan Dietrich , Sabine Kieser , Pramod Acharya
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)
摘要翻译：用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle）信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间时钟信号（CLK）的周期时间（tcycle）

2. 发明授权

US07120818B2 Method and device for data transfer 有权
公开(公告)号：US07120818B2
公开(公告)日：2006-10-10
申请号：US10103517
申请日：2002-03-22
申请人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
发明人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
IPC分类号： G06F1/04
CPC分类号： G11C7/1078 , G06F13/4068 , G11C7/1051 , G11C7/1057 , G11C7/1084
摘要： Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

3. 发明授权

US06614700B2 Circuit configuration with a memory array 有权
公开(公告)号：US06614700B2
公开(公告)日：2003-09-02
申请号：US10116826
申请日：2002-04-05
申请人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
发明人： Stefan Dietrich , Peter Schrögmeier , Sabine Kieser , Christian Weis
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/22
摘要： The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

4. 发明授权

US06542389B2 Voltage pump with switch-on control 失效
公开(公告)号：US06542389B2
公开(公告)日：2003-04-01
申请号：US10046378
申请日：2001-10-19
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
IPC分类号： H02M307
CPC分类号： H02M3/07
摘要： The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

5. 发明授权

US06882554B2 Integrated memory, and a method of operating an integrated memory 失效
标题翻译：集成存储器以及操作集成存储器的方法
公开(公告)号：US06882554B2
公开(公告)日：2005-04-19
申请号：US10287501
申请日：2002-11-04
申请人： Michael Markert , Christian Weis , Sabine Kieser , Stefan Dietrich , Peter Schrögmeier , Thomas Hein
发明人： Michael Markert , Christian Weis , Sabine Kieser , Stefan Dietrich , Peter Schrögmeier , Thomas Hein
IPC分类号： G11C7/06 , G11C11/408 , G11C11/4091 , G11C5/06
CPC分类号： G11C7/067 , G11C11/4087 , G11C11/4091 , G11C2207/105
摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.
摘要翻译：集成存储器具有用于激活读/写放大器的行线，列线和列选择线。在每种情况下，一组预定数量的存储单元属于行和列地址。此外，存储器具有对应于预定数量的多个连接焊盘。一组存储器单元中的每个存储器单元与一个连接焊盘相关联。设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。对于两个或更多列地址，其中一列列选择行被激活。因此，可以减小存储芯片上的延迟时间和线路长度。

6. 发明授权

US06847581B2 Integrated circuit and method for operating the integrated circuit 有权
标题翻译：用于集成电路的集成电路和方法
公开(公告)号：US06847581B2
公开(公告)日：2005-01-25
申请号：US10340989
申请日：2003-01-13
申请人： Pramod Acharya , Peter Schrögmeier , Stefan Dietrich , Christian Weis
发明人： Pramod Acharya , Peter Schrögmeier , Stefan Dietrich , Christian Weis
IPC分类号： H03K5/00 , H03K5/13 , G11C29/00
CPC分类号： H03K5/13 , H03K5/00006
摘要： An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.
摘要翻译：集成电路包括具有至少一个第一和第二输入的处理电路，连接到用于获得控制时钟的连接。第一和第二输入用于接收至少一个第一和第二时钟信号，每个第一和第二时钟信号各自从控制时钟导出并相对于彼此相位移位。第三时钟信号从第一和第二时钟信号产生，并且处于比用于控制电路的操作的控制时钟的频率更高的频率。第三个时钟信号在输出端输出。由于第三时钟信号的频率大于控制时钟的频率，所以可以通过使用测试单元向较低频率提供控制时钟来在其全频范围内操作该电路。

7. 发明授权

US06359832B2 Method and circuit configuration for read-write mode control of a synchronous memory 有权
标题翻译：用于同步存储器的读写模式控制的方法和电路配置
公开(公告)号：US06359832B2
公开(公告)日：2002-03-19
申请号：US09773222
申请日：2001-01-31
申请人： Stefan Dietrich , Sabine Schöniger , Peter Schrögmeier , Christian Weis
发明人： Stefan Dietrich , Sabine Schöniger , Peter Schrögmeier , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/12 , G11C11/4094
摘要： A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.
摘要翻译：描述了一种读写模式控制方法，其中可以通过在第一电路部分中进行具有自动预充电的读取指令来缩短读取处理期间的等待时间。第一电路部分与用于执行写指令的第二电路部分分开，因为存储器控制器不需要在写指令和相关联的激活信号之间插入任何等待周期。

8. 发明授权

US06396755B2 Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory 有权
标题翻译：具有行访问控制的集成存储器，用于激活和预充行行，以及操作这种存储器的方法
公开(公告)号：US06396755B2
公开(公告)日：2002-05-28
申请号：US09864978
申请日：2001-05-24
申请人： Stefan Dietrich , Sabine Schöniger , Peter Schrögmeier , Christian Weis
发明人： Stefan Dietrich , Sabine Schöniger , Peter Schrögmeier , Christian Weis
IPC分类号： G11C700
CPC分类号： G11C8/00
摘要： An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.
摘要翻译：集成存储器具有各自连接到行线的存储单元，以选择存储器单元之一和列线来读取或写入数据信号。行访问控制器用于激活行行之一以选择存储器单元之一并且控制预充电操作以对行行之一进行预充电。预充电命令启动预充电操作。激活的行线的预充电操作在数据信号的读取或写入已经完成时由行存取控制器触发，并且当激活行至少必须被激活的定义的时间间隔已经过去时。结果，以自动调节的方式控制激活的行线的预充电操作。还提供了一种操作集成存储器的方法。

9. 发明授权

US06388944B2 Memory component with short access time 有权
标题翻译：具有访问时间短的内存组件
公开(公告)号：US06388944B2
公开(公告)日：2002-05-14
申请号：US09773221
申请日：2001-01-31
申请人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
发明人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C7/1069
摘要： A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.
摘要翻译：具有短数据访问时间的存储器芯片通过相对于单元阵列条的中心对中开关来限制远离输出放大器的本地数据线条上的位的传播时间，其中开关是本地数据线和主数据线。

10. 发明授权

US06272035B1 Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US06272035B1
公开(公告)日：2001-08-07
申请号：US09618124
申请日：2000-07-17
申请人： Stefan Dietrich , Peter Schrögmeier , Torsten Partsch , Christian Weis
发明人： Stefan Dietrich , Peter Schrögmeier , Torsten Partsch , Christian Weis
IPC分类号： G11C506
CPC分类号： G11C7/1012 , G11C7/1006 , G11C7/1042 , G11C7/1066 , G11C7/1072
摘要： A memory has an input circuit, which is provided adjacent to two groups of memory cells and via which two global data lines are connected to two local data lines. The memory has two operating states during which it feeds the data provided on the global data lines in respective different assignments to the two local data lines.
摘要翻译：存储器具有输入电路，其被设置为与两组存储器单元相邻，并且两条全局数据线经由该存储器单元连接到两条本地数据线。存储器具有两个操作状态，在该操作状态期间，它将提供在全局数据线上的数据分别馈送到两个本地数据线。

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