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1. 发明专利

JPS60192396A Printed board unit connecting structure 失效
标题翻译：印刷板单元连接结构
公开(公告)号：JPS60192396A
公开(公告)日：1985-09-30
申请号：JP4717684
申请日：1984-03-14
申请人： Fujitsu Ltd , Nippon Telegraph & Telephone , Nippon Electric Co , Hitachi Ltd , Oki Electric Ind Co Ltd
发明人： MORI SHIGEKI , ANDOU YASUHIRO , YASUDA TOYOJI , ABE MIKIO , KATABUCHI KENJIROU , NAKAGAWA HIDEKAZU
IPC分类号： H05K7/14 , H05K7/18

2. 发明专利

JPS56107664A SIGNAL TRANSMISSION SYSTEM 失效
公开(公告)号：JPS56107664A
公开(公告)日：1981-08-26
申请号：JP1044880
申请日：1980-01-30
申请人： NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： YASUDA TOYOJI , TAKEI TADASHI , FUHA MASAHIRO , USUI IKUO , OBARA SHINICHIROU
IPC分类号： H03M5/08 , H04J3/06 , H04L25/49
摘要： PURPOSE:To enable to completely change the receiving circuit to an integrated circuit, by constituting the system so that binary information, frame information and clock information can be transmitted by means of one transmission circuit. CONSTITUTION:When a binary signal is transmitted, the signal is inverted (for instance, the signal is made to rise) in the specified direction at the start point of the unit width T of a constant period, and corresponding to the contents (''0'', ''1'') of the binary information, the signal is inverted (for instance, the signal is made to brake) in the opposite direction of said direction by shorter width than width of T/2 (for instance, it is made ''0''), or longer width (for instance, it is made ''1''), and it is transmitted. On the other hand, when the frame information F is transmitted, the inversion of signal is halted (the signal is not made to rise or break) as to 1 signal of unit width T, and the information is transmitted. The receiving circuit generates the clock CLI of the same phase as the rise (or breaking) point of the transmission signal, the CLII (T/2 delay phase) and the CLIII (T delay phase), and the binary information, the frame information and the clock information are detected from the CLI and the transmission signal, the negative signal of the CLIII and the logical product of the CLI, and the logical sum of the CLI and III, respectively.

3. 发明专利

JPS58151154A TRANSMISSION SYSTEM BETWEEN DEVICES 失效
公开(公告)号：JPS58151154A
公开(公告)日：1983-09-08
申请号：JP3240882
申请日：1982-03-03
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： KATAYAMA TADASHI , TSUBOI TOSHINORI , YASUDA TOYOJI , TAKAYAMA HIDEAKI , ONO CHIYUUKICHI , MURAKAMI KOUZOU
IPC分类号： H03M5/04 , H04L25/02 , H04L25/49
摘要： PURPOSE:To obtain a digital signal transmission circuit excellent in SN ratio, by probiding a PM encoding circuit for a transmission section for balanced transmission in suppressing DC components, and monitoring the relation of complementary of PM codes at a signal reproducing and monitoring circuit of a reception section. CONSTITUTION:Transformers 31, 32 are provided at the post-position of a cable driver element 10 of the transmission section and at the pre-position of a cable receiver element 20 of a reception section to two devices 1, 2 having different grounding systems to separate ground potentials EA, EB and the reduction in noise margin of each element is prevented. Further, an exclusive logical sum element 11, a clock pulse forming section 12 and a flip-flop 13 are provided at the pre-stage of the element 10 to provide complementary logical values by using a clock pulse of duty cycle 50%. Thus, a digital signal is converted into the PM (phase modulation) code consisting of two-bit of ''01'' or ''10'', and the DC components are suppressed, allowing to perform balanced transmission via the transformers 31, 32 and the cable 3.

4. 发明专利

JPS56158554A BALANCING TRANSMISSION MATCHING AND TERMINATING METHOD 失效
公开(公告)号：JPS56158554A
公开(公告)日：1981-12-07
申请号：JP6259280
申请日：1980-05-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： MATSUNAGA HIROSHI , YASUDA TOYOJI , TAKEI TADASHI , MASUDA KATSUHIRO , USUI IKUO
IPC分类号： H04B3/00 , H03K19/0175 , H04B3/30 , H04B3/32 , H04L25/02
摘要： PURPOSE:To prevent the production of reflection waves between two wires and ground of a balanced transmission line and to enable accurate information transfer, by connecting resistance and a capacitor in series between the neutral point of the termination resistance and ground, in a DC coupling balanced transmission line. CONSTITUTION:At both the ends of a balanced transmission line B, the values of resistances R2-4 and of a capacitor C are selected so that a characteristic impedance Zb between two wires and a characteristic impedance Zu between two wires and ground can be matched with the matching and terminating circuit. Thus, against a signal or external noise produced between two wires and ground of a balanced transmission line B, negative reflection waves have no possibility to the produced, and the output impedance of a transmission circuit DV is avoided from being a low value.

5. 发明专利

JPS56152357A OFFSET POTENTIAL APPLYING METHOD 失效
公开(公告)号：JPS56152357A
公开(公告)日：1981-11-25
申请号：JP5508380
申请日：1980-04-25
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： FUHA MASAHIRO , YASUDA TOYOJI , TAKEI TADASHI , YOSHIDA SUMIO , OBARA SHINICHIROU
IPC分类号： H04B1/74 , H04B3/00 , H04B3/40 , H04L25/02
摘要： PURPOSE:To settle the output potential of the receiving circuit to a constant value, by connecting series resistances between both ends of the matching terminating resistance, which is connected between two lines of the balanced transmission line, and differential input terminals of the receiving circuit and by applying the offset potential across differential input terminals. CONSTITUTION:One end of matching terminating resistance 5 is connected to differential input terminal 6 of receiving circuit 8 through series resistance 10. The other end of resistance 5 is connected to differential input terminal 7 of circuit 8 through series resistance 11. At the normal operation time, the signal level from transmission circuit 1 and the noise level generated on balanced transmission line 4 are attenuated by resistances 10 and 11. For the release of transmission line 4, the short-circuit fault, or the fault or power break of circuit 1, the output potential at output terminal 9 of circuit 8 is settled to a constant potential because a constant offset potential is applied across terminals 6 and 7 of circuit 8.

6. 发明专利

JPS56152356A MATCHED TERMINATING METHOD FOR DIRECT CURRENT COUPLING BALANCED BUS 失效
公开(公告)号：JPS56152356A
公开(公告)日：1981-11-25
申请号：JP5498480
申请日：1980-04-25
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NIPPON ELECTRIC CO , HITACHI LTD
发明人： MATSUNAGA HIROSHI , YASUDA TOYOJI , TAKEI TADASHI , FUHA MASAHIRO , MASUDA TAKASHI
IPC分类号： H04B3/00 , H03K19/0175 , H04B3/40 , H04L25/02
摘要： PURPOSE:To prevent the occurrence of the reflected wave, by connecting terminating resistance circuits matched to characteristic impedances between two lines and between two lines to ground of the balanced transmission line respectively and by giving the output settling potential of the receiving circuit to two lines. CONSTITUTION:Both ends of balanced transmission line B for information transfer between transmission circuit DV and receiving circuit RC are terminated by matched terminating resistance circuits consisting of resistances R4, R5 and R6 respectively. Potential +E is applied to one ends of resistances R5 and R6. Characteristic impedances Zb and Zu between two lines and between two lines to ground of balanced transmission line B are matched. The impedance at the view between two lines of transmission line B and the impedance at the view between two lines to ground are equal to impedances Zb and Zu respectively. As a result, the signal generated between two lines to ground and the reflected wave for the external noise are prevented.

7. 发明专利

JPH0336791A MULTILAYER CIRCUIT CERAMIC BOARD 失效
公开(公告)号：JPH0336791A
公开(公告)日：1991-02-18
申请号：JP17157289
申请日：1989-07-03
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YASUDA TOYOJI , KON TAICHI , ONO YUKIHARU
IPC分类号： H05K3/46
摘要： PURPOSE:To increase the density of viahole pitch and to decrease an electric resistance of a voltage supply layer by increasing the viahole pitch of a meshlike power source layer requiring a large current than that of a meshlike power source layer not requiring a large current. CONSTITUTION:A plurality of meshlike power source layers E1, E2, E3, D4, D5 are disposed in division of layers in a laminated ceramic board 1. The layers E1, E2, E3 are disposed on the rear face side of the board 1, and used as power source layers requiring a large current. On the other hand, the layers D4, D5 are disposed on the front face side of the board 1, and used as power source layers not requiring a large current. They are connected to signal interconnections S or the layers D4, D5 or E1, E2, E3 through viaholes 2S, 2D, 2E. Here, the viahole pitch PE of the layers E1, E2, E3 is increased twice as large as that PD of the layers D4, D5.

8. 发明专利

JPH02232992A ELECTRONIC CIRCUIT MODULE 失效
公开(公告)号：JPH02232992A
公开(公告)日：1990-09-14
申请号：JP5350089
申请日：1989-03-06
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SASAKI SHINICHI , YASUDA TOYOJI , KON TAICHI
IPC分类号： H05K7/20 , H05K3/46
摘要： PURPOSE:To improve an electronic circuit module of this design in heat dissipating property without deteriorating it in wiring housing property by a method wherein two or more heat transfer bodies excellent in thermal conductivity are provided to a polyimide interlaminar insulating film. CONSTITUTION:Many heat transfer rods 15 are provided to a part of a polyimide multilayer wiring layer 5 so as to reach to the surface of a ceramic multilayer wiring board 1. The rod 15 is formed of a material such as copper or the like excellent in thermal conductivity, and an LSI chip 8 is mounted on the part where the rods 15 are provided. Therefore, heat released from the chip 8 is efficiently conducted to the board 1 passing through the rods 15. The rod 15 is made as minute as a viahole used for the interlaminar connection of the layer 5, whereby a signal and a power wiring 7a and 7b, are provided even inside a polyimide interlaminar insulating film 6. Therefore, an electronic circuit module of this design can be improved in heat dissipating property without deteriorating it in wiring housing property.

9. 发明专利

JPH0254999A ULTRA COMPACT PARTS ADHESION MOUNTING DEVICE 失效
公开(公告)号：JPH0254999A
公开(公告)日：1990-02-23
申请号：JP20568988
申请日：1988-08-20
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YASUDA TOYOJI , KON TAICHI , AKIMA KAZUICHI
IPC分类号： H05K13/04 , H05K3/34
摘要： PURPOSE:To enable a parts to be mounted to a desired position accurately by retaining a needle for adhering an adhesive and a needle for sucking the parts aslant in reference to the surface of a wiring board for mounting the parts and applying the adhesive and sucking and pressing the parts while performing observation directly above the wiring board using a microscope. CONSTITUTION:First of all, the tip of a needle for adhering an adhesive 16 of a fine-moving head 6 is moved to the upper part of a well of adhesive 5 and a fine-moving screw 16 is operated to allow the needle 16 to be lowered to the inside the adhesive well and to be lifted by adhering the adhesive, thus moving closer to a position where parts are mounted. Then, by observing a microscope 15, the fine-moving screws 181-183 are rotated to allow the needle to be lowered to a specified position. Then, a parts 3 is subject to vacuum suction onto a needle for suction parts 20 where the needle tip is cut diagonally from a parts supply base 12 for retention and positioning is performed by the microscope 15, thus enabling the parts 3 to be pressed and adhered to a location where an adhesive 4 is applied.

10. 发明专利

JPS5511351A SUBSTRATE FOR PRINTED CIRCUIT BOARD 失效
公开(公告)号：JPS5511351A
公开(公告)日：1980-01-26
申请号：JP8402078
申请日：1978-07-12
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SUGITA ETSUJI , YASUDA TOYOJI , MATSUMOTO TADASHI
IPC分类号： B32B15/04 , B32B5/00 , B32B15/08 , H05K1/03

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