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1. 发明专利

JP2003318405A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003318405A
公开(公告)日：2003-11-07
申请号：JP2002124180
申请日：2002-04-25
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MAEDA SHIGENOBU , MATSUMOTO TAKUJI , IWAMATSU TOSHIAKI , IPPOSHI TAKASHI
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7841 , H01L29/78615 , H01L29/78654 , Y10S438/981
摘要： PROBLEM TO BE SOLVED: To provide a SOI device where a body is fixed and a high speed and stable operation is realized. SOLUTION: A gate insulating film 11 whose thickness is 1 to 5 nm is disposed between a part except for a gate contact pad GP in a gate electrode 12 and a SOI layer 3. A gate insulating film 110 whose thickness is 5 to 15 nm is arranged between the gate contact pad GP and the SOI layer 3. The gate insulating film 11 and the gate insulating film 110 continue. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种身体固定并实现高速稳定操作的SOI器件。解决方案：栅极电极12和SOI层3之间的栅极接触焊盘GP之外的部分之间设置厚度为1〜5nm的栅极绝缘膜11.栅极绝缘膜110的厚度为5〜在栅极接触焊盘GP和SOI层3之间设置15nm。栅极绝缘膜11和栅极绝缘膜110继续。版权所有（C）2004，JPO

2. 发明专利

JP2003318200A Thin-film transistor and its manufacturing method 审中-公开
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：JP2003318200A
公开(公告)日：2003-11-07
申请号：JP2003159100
申请日：2003-06-04
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MAEDA SHIGENOBU
IPC分类号： H01L29/786 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To suppress a variance of threshold voltage V
th of a TFT.
SOLUTION: The V
th of the TFT wherein a gate insulation film is formed and rinsed with water and after it is left for a specified time a channel polysilicon is formed, increases sharply around one hour later and a variance becomes large. It is because an impurity (e.g. boron) on the gate insulation film of the TFT is once rinsed off by water rinsing, however, after rinsing is completed and some time passes, an impurity such as boron in an atmosphere is stuck again. In the TFT 300 hours later after water rinsing, a difference in concentration in the same chip concerning a boron concentration of the channel polysilicon (difference in concentration of in-plane channel boron) is about 3×10
18 /cm
2 , however, that of the TFT one hour later after water rinsing decreases to 1×10
18 /cm
2 .
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：抑制TFT的阈值电压V 的变化。
解决方案：TFT的V ，其中形成栅极绝缘膜并用水冲洗，并且在其形成沟道多晶硅一段特定时间后，大约在1小时后急剧增加并且方差变大。这是因为TFT的栅极绝缘膜上的杂质（例如硼）被水冲洗一次，然而，在漂洗完成并且经过一段时间之后，再次卡住大气中的硼等杂质。在水冲洗300小时后的TFT中，与通道多晶硅的硼浓度（面内通道硼的浓度的差异）相同的芯片中的浓度差为约3×10 -6 / / cm 2 ，然而，水洗后一小时后的TFT的浓度降至1×10 18 / cm 2 。版权所有（C）2004，JPO

3. 发明专利

JP2003037273A Tft 审中-公开
标题翻译： TFT
公开(公告)号：JP2003037273A
公开(公告)日：2003-02-07
申请号：JP2002154405
申请日：2002-05-28
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MAEDA SHIGENOBU
IPC分类号： H01L27/11 , H01L21/8244 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a TFT which meets reliability required in-BT stress condition, based on the established reliability evaluation method which is related to deterioration of TFT characteristics under-BT stress.
SOLUTION: The TFT used for an SRAM memory cell comprises the channel layer of a silicon thin film and a gate insulating film of a silicon oxide film. The threshold voltage is shifted toward the positive voltage side, in advance by the amount the threshold voltage is shifted toward the negative voltage side in burn-in test.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种满足BT应力条件下的可靠性的TFT，其基于与BT特性在BT应力下的劣化相关的可靠性评估方法。解决方案：用于SRAM存储单元的TFT包括硅薄膜的沟道层和氧化硅膜的栅极绝缘膜。在老化测试中，阈值电压预先向阈值电压向负电压侧移动的量向正电压侧移动。

4. 发明专利

JP2003068869A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003068869A
公开(公告)日：2003-03-07
申请号：JP2001254516
申请日：2001-08-24
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MAEDA SHIGENOBU , TAKASHINO HIROYUKI , OKA SHUNEI
IPC分类号： H01L29/78 , H01L21/265 , H01L21/74 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device of the structure in which the respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated, and a method of obtaining the same. SOLUTION: An NMOS transistor Q1 and a PMOS transistor Q2 which are respectively formed in the NMOS forming region A1 and PMOS forming region A2 have P pocket regions 17 and N pocket regions 27 at the regions near the extension areas 14e and 24e of the N source/drain region 14 and P source/drain region 24. Meanwhile, an N-type variable capacitance C1 and P-type variable capacitance C2 respectively formed at an N-type variable capacitance forming region A3 and a P-type variable capacitance forming region A4 do not have inverse conductivity type regions adjacent to the leadout electrode regions corresponding to the P pocket region 17 and N pocket region 27.
摘要翻译：要解决的问题：为了获得绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件及其获得方法。解决方案：分别形成在NMOS形成区域A1和PMOS形成区域A2中的NMOS晶体管Q1和PMOS晶体管Q2在N'的延伸区域14e和24e附近的区域具有P个凹穴区域17和N个凹穴区域27， +源极/漏极区14和P +源极/漏极区24.同时，分别形成在N型可变电容形成区A3和P-型可变电容形成区A3的N型可变电容C1和P型可变电容C2，类型可变电容形成区域A4不具有与对应于P <！ - SIPO - >口区域17和N'口区域27的引出电极区域相邻的反向导电型区域。

5. 发明授权

US6424010B2 Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage 失效
标题翻译：制造具有降低的功耗而不降低源/漏击穿电压的半导体器件的方法
公开(公告)号：US6424010B2
公开(公告)日：2002-07-23
申请号：US16990398
申请日：1998-10-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU , YAMAGUCHI YASUO , IWAMATSU TOSHIAKI
IPC分类号： H01L21/00 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/786 , H01L29/76 , H01L23/58 , H01L23/62
CPC分类号： H01L29/78696 , H01L21/76297 , H01L21/84 , H01L27/1203 , H01L29/404 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.
摘要翻译：在硅衬底上形成SOI层，其间具有掩埋绝缘层。形成SOI-MOSFET，其包括形成为在SOI层处限定沟道形成区域的漏极区域和源极区域，并且包括与沟道形成区域相对的栅极电极层，其间具有绝缘层。形成场屏蔽（FS）隔离结构以具有与漏极区域和源极区域的边缘部分附近的SOI层的区域相对的FS板，并且将SOI-MOSFET与其他电极隔离通过向FS板施加规定的电位以固定与FS板相对的SOI层的区域的电位的元件。通道形成区域包括两侧的边缘部分和沿通道宽度方向的边缘部分之间的中心部分，并且规定区域的边缘处的通道长度小于中心部分处的通道长度。

6. 发明公开

EP0905789A4 SEMICONDUCTOR DEVICE HAVING SOI STRUCTURE AND METHOD FOR MANUFACTURING THE DEVICE 失效
标题翻译：根据上述制造SOI结构和工艺半导体器件
公开(公告)号：EP0905789A4
公开(公告)日：1999-08-25
申请号：EP96917698
申请日：1996-06-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMAGUCHI YASUO , MAEDA SHIGENOBU , KIM ILJONG
IPC分类号： H01L21/265 , H01L21/336 , H01L21/339 , H01L21/425 , H01L27/12 , H01L29/786
CPC分类号： H01L29/78696 , H01L21/26506 , H01L21/26586 , H01L27/12 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78621
摘要： A semiconductor device having such an SOI structure that diffusion of impurities from the source/drain regions into the end portions of a silicon layer below the gate electrode is prevented. In this semiconductor device, nitrogen (8) is introduced into at least one of the source/drain regions (14) and the end portions of the semiconductor layer (3). A first concentration peak of the nitrogen concentration profile is at least in one of the end portions of the regions (14) in the direction where the electrode (12) extends and the end portions of the layer (3). Because of the nitrogen concentration profile, point defects, etc., which mediate the diffusion of impurities are trapped, and consequently the diffusion of impurities from the regions (14) is suppressed. Therefore, abnormal leakage current, etc., are prevented.

7. 发明专利

DE19845294B4 未知
公开(公告)号：DE19845294B4
公开(公告)日：2005-11-03
申请号：DE19845294
申请日：1998-10-01
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU
IPC分类号： H01L27/04 , H01L21/822 , H01L23/485 , H01L29/786 , H01L23/60 , H01L23/50
摘要： A semiconductor device for protecting an electronic circuit from a surge and a method for manufacturing the semiconductor device are obtained. The semiconductor device comprises a p-type semiconductor substrate 13, an insulator 14 enclosing a SOI layer 111 on which an electronic circuit is formed, and provided on the semiconductor substrate 13, a bonding pad 121 conducted to the SOI layer 111 through a wiring 113, and a bonding region 12 including the bonding pad 121 and an opening 122 having a bottom to which the semiconductor substrate 13 is exposed. A bonding wire 3 is bonded to the bonding region 12.

8. 发明专利

FR2831713B1 未知
公开(公告)号：FR2831713B1
公开(公告)日：2005-09-30
申请号：FR0214877
申请日：2002-11-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO TAKUJI , SAYAMA HIROKASU , MAEDA SHIGENOBU
IPC分类号： H01L21/822 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786 , H04L1/16 , H04L29/08
摘要： A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film ( 6 ) is formed partially on the upper surface of a silicon layer ( 3 ). A gate electrode ( 7 ) of polysilicon is formed partially on the silicon oxide film ( 6 ). A portion of the silicon oxide film ( 6 ) underlying the gate electrode ( 7 ) functions as a gate insulation film. A silicon nitride film ( 9 ) is formed on each side surface of the gate electrode ( 7 ), with a silicon oxide film ( 8 ) therebetween. The silicon oxide film ( 8 ) and the silicon nitride film ( 9 ) are formed on the silicon oxide film ( 6 ). The width (W 1 ) of the silicon oxide film ( 8 ) in a direction of the gate length is greater than the thickness (T 1 ) of the silicon oxide film ( 6 ).

9. 发明专利

FR2769406B1 未知
公开(公告)号：FR2769406B1
公开(公告)日：2004-10-22
申请号：FR9806097
申请日：1998-05-14
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWAMATSU TOSHIAKI , YAMAGUCHI YASUO , IPPOSHI TAKASHI , MAEDA SHIGENOBU , HIRANO YUUICHI
IPC分类号： H01L21/02 , H01L21/84 , H01L27/12 , H01L21/316
摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.

10. 发明专利

DE19842441B4 未知
公开(公告)号：DE19842441B4
公开(公告)日：2004-07-29
申请号：DE19842441
申请日：1998-09-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAEDA SHIGENOBU , NISHIMURA TADASHI , TSUTSUMI KAZUHITO , MAEGAWA SHIGETO , HIRANO YUUICHI
IPC分类号： H01L21/60 , H01L23/485 , H01L23/556 , H01L27/12 , H01L29/786 , H01L23/50
摘要： A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

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