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1. 发明申请

WO2020068344A1 MEMORY POOLING BETWEEN SELECTED MEMORY RESOURCES VIA A BASE STATION 审中-公开
公开(公告)号：WO2020068344A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/048534
申请日：2019-08-28
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P.
IPC分类号： G06F13/16 , G06F3/06 , G06F12/14 , G06F13/18 , H04W4/44
摘要： Apparatuses, systems, and methods related to memory pooling between selected memory resources via a base station are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first memory resource, a first processor coupled to the first memory resource, and a wireless base station coupled to the first processor. The first memory resource, the first processor, and the base station are configured to enable formation of a memory pool between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station.

2. 发明申请

WO2020131327A1 APPARATUSES AND METHODS FOR ORGANIZING DATA IN A MEMORY DEVICE 审中-公开
公开(公告)号：WO2020131327A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/063373
申请日：2019-11-26
申请人： MICRON TECHNOLOGY, INC.
发明人： HUSH, Glen E. , BOEHM, Aaron P. , LUO, Fa-Long
IPC分类号： G06F3/06 , G06F13/16
摘要： Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

3. 发明申请

WO2020068891A1 SHARING A MEMORY RESOURCE AMONG PHYSICALLY REMOTE ENTITIES 审中-公开
公开(公告)号：WO2020068891A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/052816
申请日：2019-09-25
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P.
IPC分类号： G06F13/16 , G06F3/06 , G06F12/14
摘要： Apparatuses, systems, and methods related to sharing a memory resource among physically remote entities are described. A system sharing a memory resource among physically remote entities may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first vehicle configured to determine an availability of processing resources or memory capacity, or both, at the first vehicle based at least in part on a current operating mode of the first vehicle, receive a request from a second vehicle to use at least a portion of the processing resources or the memory capacity, or both, to perform a processing operation at a second vehicle, wherein the request from the second vehicle is associated with insufficient processing capability or memory capacity, or both, at the second vehicle, and perform at least a portion of the processing operation or allow access to the available memory capacity, or both, at the first vehicle in response to the request and based at least in part on determining the availability of the processing resources or the memory capacity, or both.

4. 发明公开

EP3867760A1 ERROR CORRECTION MANAGEMENT FOR A MEMORY DEVICE 审中-实审
公开(公告)号：EP3867760A1
公开(公告)日：2021-08-25
申请号：EP19873424.6
申请日：2019-10-04
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P. , SCHAEFER, Scott E.
IPC分类号： G06F11/10 , G11C29/52

5. 发明公开

EP3857392A1 SHARING A MEMORY RESOURCE AMONG PHYSICALLY REMOTE ENTITIES 审中-公开
公开(公告)号：EP3857392A1
公开(公告)日：2021-08-04
申请号：EP19866574.7
申请日：2019-09-25
申请人： Micron Technology, Inc.
发明人： BOEHM, Aaron P.
IPC分类号： G06F13/16 , G06F3/06 , G06F12/14

6. 发明申请

WO2020131667A1 APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE 审中-公开
公开(公告)号：WO2020131667A1
公开(公告)日：2020-06-25
申请号：PCT/US2019/066460
申请日：2019-12-16
申请人： MICRON TECHNOLOGY, INC.
发明人： HUSH, Glen E. , BOEHM, Aaron P. , LUO, Fa-Long
IPC分类号： G11C7/10 , G11C7/06
摘要： Systems, apparatuses and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

7. 发明申请

WO2020068610A1 ACCESSING A MEMORY RESOURCE AT ONE OR MORE PHYSICALLY REMOTE ENTITIES 审中-公开
公开(公告)号：WO2020068610A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/052342
申请日：2019-09-23
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P.
IPC分类号： G06F9/50 , G06F15/16 , H04B1/16
摘要： Apparatuses, systems, and methods related to accessing a memory resource at one or more physically remote entities are described. A system accessing a memory resource at one or more physically remote entities may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first vehicle configured to determine that a processing capability or a memory capacity, or both, at the first vehicle is insufficient to perform a processing operation at the first vehicle, identify additional processing resources or additional memory capacity, or both, at a second vehicle that is in wireless communication with the first vehicle based at least in part on determining that the processing capability or the memory capacity, or both, at the first vehicle is insufficient, and perform the processing operation at the first vehicle using the additional processing resources or the additional memory capacity, or both.

8. 发明申请

WO2019152182A1 DETERMINATION OF A MATCH BETWEEN DATA VALUES STORED BY SEVERAL ARRAYS 审中-公开
公开(公告)号：WO2019152182A1
公开(公告)日：2019-08-08
申请号：PCT/US2019/013613
申请日：2019-01-15
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P.
IPC分类号： G06F11/16 , G06F11/20
摘要： Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.

9. 发明申请

WO2021206958A1 TARGETED COMMAND/ADDRESS PARITY LOW LIFT 审中-公开
公开(公告)号：WO2021206958A1
公开(公告)日：2021-10-14
申请号：PCT/US2021/024870
申请日：2021-03-30
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P. , SCHAEFER, Scott E.
IPC分类号： G11C29/42 , G11C29/52 , G06F11/10 , G06F3/06
摘要： Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.

10. 发明申请

WO2020081262A1 ERROR CORRECTION MANAGEMENT FOR A MEMORY DEVICE 审中-公开
公开(公告)号：WO2020081262A1
公开(公告)日：2020-04-23
申请号：PCT/US2019/054763
申请日：2019-10-04
申请人： MICRON TECHNOLOGY, INC.
发明人： BOEHM, Aaron P. , SCHAEFER, Scott E.
IPC分类号： G06F11/10 , G11C29/52
摘要： Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

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