专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008100415A3 NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储系统
公开(公告)号：WO2008100415A3
公开(公告)日：2008-11-27
申请号：PCT/US2008001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD , WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
发明人： WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
IPC分类号： G06F11/10
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器读/写。 X是大于或等于1的整数。

2. 发明申请

WO2008100415A2 NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：非易失性存储器系统
公开(公告)号：WO2008100415A2
公开(公告)日：2008-08-21
申请号：PCT/US2008001669
申请日：2008-02-08
申请人： MARVELL WORLD TRADE LTD , WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
发明人： WU ZINING , NGUYEN LAU , SUTARDJA PANTAS , LEE CHI-KONG , YOON TONY
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0661 , G06F11/1068 , G06F12/0246
摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.
摘要翻译：非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控制模块。该系统还包括NV存储器，其包括X阵列，其包括尺寸与编码的逻辑数据结构不同的物理数据结构。存储器控制模块根据编码的逻辑数据结构从NV存储器写入/读取。 X是大于或等于1的整数。

3. 发明申请

WO2009039222A3 FLEXIBLE SEQUENCER DESIGN ARCHITECTURE FOR SOLID STATE MEMORY CONTROLLER 审中-公开
标题翻译：用于固态存储器控制器的灵活的序列设计架构
公开(公告)号：WO2009039222A3
公开(公告)日：2009-06-04
申请号：PCT/US2008076741
申请日：2008-09-17
申请人： MARVELL WORLD TRADE LTD , SHIN HYUNSUK , LEE CHI KONG , YOON TONY
发明人： SHIN HYUNSUK , LEE CHI KONG , YOON TONY
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F13/1668 , G06F3/061 , G06F3/0659 , G06F3/0688
摘要： A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.
摘要翻译：用于控制对固态存储器件的访问的方法和装置，其可以允许以最少的固件干预来访问固态存储器设备的最大并行性。为了减少主机时间的浪费，可以将多个闪存设备连接到每个通道。通过允许每个存储器件分开操作，可以使用作业/描述符架构来增加并行性。可以使用作业来表示读取，写入或擦除操作。当固件想要将作业分配给设备时，它可以发布描述符，其可以包含关于目标通道，目标设备，操作类型等的信息。固件可以提供描述符而不等待来自存储器的响应设备，并且可以连续地发出几个作业以形成作业队列。固件完成编程描述符后，定序器可以处理剩余的工作，以便固件可以专注于其他任务。

4. 发明申请

WO2010045445A2 ARCHITECTURE FOR DATA STORAGE SYSTEMS 审中-公开
标题翻译：数据存储系统的体系结构
公开(公告)号：WO2010045445A2
公开(公告)日：2010-04-22
申请号：PCT/US2009060823
申请日：2009-10-15
申请人： MARVELL WORLD TRADE LTD , YOON TONY , AU SIU-HUNG FRED
发明人： YOON TONY , AU SIU-HUNG FRED
IPC分类号： G06F13/16
CPC分类号： G06F5/12 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1673
摘要： A system includes N first-in first-out (FIFO) modules, a buffer manager module, and N input/output (I/O) modules, where N is an integer greater than 1. The buffer manager module retrieves a set of N data units from a buffer and outputs the set of N data units to the N FIFO modules in parallel at a time, respectively. The N I/O modules receive the set of N data units from the N FIFOs in parallel, respectively, and output the N data units to a medium.
摘要翻译：一个系统包括N个先进先出（FIFO）模块，一个缓冲器管理器模块和N个输入/输出（I / O）模块，其中N是大于1的整数。缓冲器管理器模块检索一组N 数据单元，并分别将该组N个数据单元并行输出到N个FIFO模块。 N个I / O模块分别并行地从N个FIFO接收一组N个数据单元，并将N个数据单元输出到介质。

5. 发明申请

WO2010045445A3 ARCHITECTURE FOR DATA STORAGE SYSTEMS 审中-公开
公开(公告)号：WO2010045445A3
公开(公告)日：2010-06-10
申请号：PCT/US2009060823
申请日：2009-10-15
申请人： MARVELL WORLD TRADE LTD , YOON TONY , AU SIU-HUNG FRED
发明人： YOON TONY , AU SIU-HUNG FRED
IPC分类号： G06F13/16
CPC分类号： G06F5/12 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1673
摘要： A system includes N first-in first-out (FIFO) modules, a buffer manager module, and N input/output (I/O) modules, where N is an integer greater than 1. The buffer manager module retrieves a set of N data units from a buffer and outputs the set of N data units to the N FIFO modules in parallel at a time, respectively. The N I/O modules receive the set of N data units from the N FIFOs in parallel, respectively, and output the N data units to a medium.

6. 发明专利

JP2010067263A Selectively accessing memory 有权
标题翻译：选择性访问记忆
公开(公告)号：JP2010067263A
公开(公告)日：2010-03-25
申请号：JP2009166080
申请日：2009-07-14
申请人： Marvell World Trade Ltd , マーベルワールドトレードリミテッド
发明人： YANG XUESHI , YOON TONY
IPC分类号： G06F12/06 , G06F12/00 , G06F12/16
CPC分类号： G06F12/0246 , G06F13/4239 , G06F2212/7202 , G06F2212/7208 , G11C11/5628 , G11C2211/5641
摘要： PROBLEM TO BE SOLVED: To provide devices, systems and methods associated with selectively accessing memory. SOLUTION: An indication indicative of whether to program fast access pages or slow access pages of a flash memory is detected. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages. COPYRIGHT: (C)2010,JPO&INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式