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    • 1. 发明申请
    • Systems and Methods for Executing Unified Process-Device-Circuit Simulation
    • 执行统一过程设备电路仿真的系统和方法
    • US20100114553A1
    • 2010-05-06
    • US12607206
    • 2009-10-28
    • Kyung Rok KimKyu-Baik ChangYoung Kwan ParkSeung Chul LeeJin Kyu Park
    • Kyung Rok KimKyu-Baik ChangYoung Kwan ParkSeung Chul LeeJin Kyu Park
    • G06F17/50G06F19/00
    • G06F17/5022G06F11/3476G06F13/105G06F17/5009
    • A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
    • 提供统一的仿真系统。 该统一模拟系统包括存储包括输入参数和环境信息的输入数据的输入数据库,统一模拟器,根据输入数据和至少一个预定模型,对半导体装置的特性执行统一的处理装置电路仿真,并输出 作为输出数据的模拟结果,以及存储输出数据的输出数据库。 统一模拟器包括:基于输入数据模拟至少一个过程并输出过程特征数据的过程仿真器;基于过程特性数据模拟至少一个设备并输出设备特征数据的设备模拟器;以及模拟电路的电路仿真器 包括所述至少一个装置。 因此,可以同时优化多个装置以优化电路特性,并且可以提供在处理和设备级别的精确规格。
    • 2. 发明授权
    • Systems and methods for executing unified process-device-circuit simulation
    • 执行统一过程设备电路仿真的系统和方法
    • US09235664B2
    • 2016-01-12
    • US12607206
    • 2009-10-28
    • Kyung Rok KimKyu-Baik ChangYoung Kwan ParkSeung Chul LeeJin Kyu Park
    • Kyung Rok KimKyu-Baik ChangYoung Kwan ParkSeung Chul LeeJin Kyu Park
    • G06F17/50G06G7/62G06F9/44G06F13/10G06F13/12G06F11/34
    • G06F17/5022G06F11/3476G06F13/105G06F17/5009
    • A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.
    • 提供统一的仿真系统。 该统一模拟系统包括存储包括输入参数和环境信息的输入数据的输入数据库,统一模拟器,根据输入数据和至少一个预定模型,对半导体装置的特性执行统一的处理装置电路仿真,并输出 作为输出数据的模拟结果,以及存储输出数据的输出数据库。 统一模拟器包括:基于输入数据模拟至少一个过程并输出过程特征数据的过程仿真器;基于过程特性数据模拟至少一个设备并输出设备特征数据的设备模拟器;以及模拟电路的电路仿真器 包括所述至少一个装置。 因此,可以同时优化多个装置以优化电路特性,并且可以提供在处理和设备级别的精确规格。
    • 10. 发明授权
    • Method for fabricating semiconductor device with negative differential conductance or transconductance
    • 制造具有负微分电导或跨导的半导体器件的方法
    • US06800511B2
    • 2004-10-05
    • US10614666
    • 2003-07-07
    • Byung Gook ParkJong Duk LeeKyung Rok Kim
    • Byung Gook ParkJong Duk LeeKyung Rok Kim
    • H01L2184
    • B82Y10/00H01L27/11H01L29/66439H01L29/66772H01L29/7613H01L29/78654Y10S438/962
    • The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate, and a tunneling device exhibiting the negative differential conductance or transconductance at room temperature can be implemented by using P+-N+ junction barriers as tunneling barriers and implanting impurity ions into a channel region so that their density is higher than the effective density of states where electrons or holes can exist thereon. Since the semiconductor device with the negative differential conductance or transconductance can be also be implemented even at room temperature, there is an advantage in that the present invention can be applied to an SRAM or a logic device using a device which can be turned on/off in response to a specific voltage. Further, according to the fabrication method of the present invention. miniaturization of the device can be easily made, and the reproducibility and the mass productivity of the process can be enhanced. Simultaneously, the gate, the source/drain and the channel regions are formed by the self-aligned process. Thus, there is another advantage in that a gate pitch can also be reduced. In addition, there is a further advantage in that the semiconductor device fabricated according to the present invention has the characteristic of a single electron transistor by using the channel region as the quantum dot and the two P+-N+ junctions as the tunneling barriers.
    • 本发明涉及一种制造具有负微分电导或跨导的半导体器件的方法。 根据本发明,可以通过使用SOI(绝缘体上硅)衬底来简化其制造工艺,并且可以通过使用P + -N +结屏障来实现在室温下具有负微分电导或跨导的隧穿装置 作为隧道势垒并将杂质离子注入沟道区域,使得其密度高于其上存在电子或空穴的状态的有效密度。 由于也可以在室温下实施具有负的差分电导或跨导的半导体器件,所以存在的优点在于本发明可以应用于使用可以被接通/断开的器件的SRAM或逻辑器件 响应于特定电压。此外,根据本发明的制造方法。 可以容易地实现器件的小型化,并且可以提高工艺的再现性和批量生产率。 同时,栅极,源极/漏极和沟道区域通过自对准工艺形成。 因此,还可以减小栅极间距的另一个优点。此外,还有一个优点是,根据本发明制造的半导体器件具有通过使用沟道区作为单电子晶体管的特性 量子点和两个P + -N +结作为隧道势垒。